Aries Embedded RISC-V on MAX10 Benutzerhandbuch - Seite 19

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RISC-V on MAX10 User Guide

5.3.2 Adding a second Uart to Qsys

Note: This section uses the Spider_S project, there may be small differences between projects that have
to be transfered.
Open the Qsys system in Intel Platform Designer. Search in the IP Catalog for "uart", select the UART
(RS-232 Serial Port) Intel FPGA IP and press Add.
The default settings are suitable for the Uart core. Connect the signals to the interconnect, for the SERV
and the VexRiscv core make sure to connect the s1 signal to the data bus. Select an unoccupied memory
range for the Memory Mapped, this example sets the base address to 0x00010300. Export the Conduit signal
to the top-level file.
The new Uart also has to be added in the top-level file, in order to do so select the menu Generate in
the Platform Designer and then Show Instantiation Template. In the dropdown menu HDL Language
select VHDL. The two new signals are uart2_rxd and uart2_txd. Open the top-level file (MX10.vhd or
Spider.vhd) in Quartus and modify the component declaration:
component
qsys0
is
(
port
clk_clk
reset_reset_n
gpio_export
uart_rxd
uart_txd
uart2_rxd
uart2_txd
);
end component
qsys0;
Chapter 5. Reference Design
:
in
std_logic;
:
in
std_logic;
:
inout
std_logic_vector(31
:
in
std_logic;
:
out
std_logic;
:
in
std_logic;
:
out
std_logic
0)
:=
(others
=>
downto
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X
);