Aries Embedded RISC-V on MAX10 Manual del usuario - Página 15
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For each of the supported MAX10 SoMs a reference design is included.
The reference design implements:
• RISC-V 32-bit Core
– PicoRV32 RV32IM (SpiderSoM-S)
– VexRiscv RV32IM (MX10-S)
– VexRiscv+Cache RV32IMAFC (MX10-U)
• On-Chip Memory (32KB, 64KB MX10-U) initialized with the firmware
• UART via PIC-USB to the host PC
• GPIO Counter on PMod J2
The MX10-U design also implements:
• DDR3 Controller connected to 512 MB RAM.
5.1 FPGA Design
The top-level file for the FPGA is depending on the project Spider.vhd or MX10.vhd. The top-level file
provides the port declaration to interface with the physical pins of the FPGA, it also declares and instantiates
the Qsys component. A process sensitive on the system clock (25 MHz) uses a counter to blink the LED
on the module once per second. The RISC-V (Qsys) system provides a binary counter on PMod J2 and
loopback for the UART interface.
Chapter 5. Reference Design
REFERENCE DESIGN
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