Aries Embedded RISC-V on MAX10 Manuel de l'utilisateur - Page 17
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Parameter
Enable Interrupts
Masked IRQ
Latched IRQ
Reset Vector
Interrupt Vector
5.1.1.3 VexRiscv
The VexRiscv core can be configured as RV32I, RV32IM without caches or as RV32IM, RV32IMAC,
RV32IMAFC with 4KB instruction and data caches.
Parameter
Reset Vector
Exception Vector
IO Region Begin
IO Region End
Core Configuration
5.2 C-Firmware
The C firmware by default will output a binary counter to the GPIO and loopback every character received
on Uart. The internal counter (or in case of the Serv the counter of the interrupt controller) will be read to
increment or decrement the binary counter value every 32th of a second. The timer will also be configured
to provide an interrupt every 2 seconds. The corresponding interrupt handler changes the direction of the
binary counter. An additional interrupt handler triggered on Uart receive will loop back the characters
received.
5.2.1 Common Files
File
Hal.c, Hal.h, Hal.S
Crt.S
FpgaConfig.h, Fpga-
Config.c
Main.c
Makefile
RiscvDef.h
Uart.c, Uart.h
bin2mif.py
link.ld
Chapter 5. Reference Design
Description
Enables the internal interrupt controller.
A 1 bit in this bitmask permanently disables the corresponding interrupt.
A 1 bit in this bitmask latches the interrupt signal (edge-triggered) instead
of operating on level sensitive interrupts.
Address loaded into the program counter when the core starts.
Address loaded into the program counter when an interrupt or execution
error occurs.
Description
Address loaded into the program counter when the core starts.
Address loaded into the program counter when an exception (interrupt or
trap) occurs.
First (inclusive) address of the uncached region; volatile memory such as
registers of external modules are required to be in this region. Does not
have an effect if no caches are used.
Last (inclusive) address of the uncached region. Does not have an effect if
no caches are used.
Specifies the implemented instruction set and caches.
Description
Hardware Abstraction Layer, provides interface to the core hardware such
as timers and interrupts
C Runtime, start-up code that initializes the core and invokes main
Configuration file that describes the Qsys RISC-V system
Entry point for the C firmware
Build file for make
Definitions for RISC-V constants
Software description and driver file for Uart
Python script, converts the binary output to a memory initalization file
Linker script, instructs the linker on how to assemble the binary.
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