Yamaha DP-U50 Manuel d'entretien - Page 21

Parcourez en ligne ou téléchargez le pdf Manuel d'entretien pour {nom_de_la_catégorie} Yamaha DP-U50. Yamaha DP-U50 46 pages. Personal sound processer
Également pour Yamaha DP-U50 : Manuel de configuration (47 pages), Manuel d'entretien (46 pages)

Yamaha DP-U50 Manuel d'entretien
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3 7 63 1515 0
IC436 : HD6417014F28
16 bit µ-COM (CPU)
No.
Port
1
PE14/DACK0//AH
2
PE15/DACK1
3
VSS
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
12
A8
13
A9
14
A10
15
A11
16
A12
17
A13
18
A14
19
A15
20
A16
21
VCC
22
A17
23
VSS
24
PB2//IRQ0//RAS
25
PB3//IRQ1//CASL
TE
L 13942296513
26
PB4//IRQ2//CASH
27
VSS
28
PB5//IRQ3/RDWR
29
PB6/A18
30
PB7/A19
31
PB8//IRQ6/A20//WAIT
32
PB9//IRQ7/A21
33
VSS
34
/RD
35
/WDTOVF
36
/WRH
37
VCC
38
/WRL
39
VSS
40
/CS1
41
/CS0
42
PA9/TCLKD//IRQ3
43
PA8/TCLKC//IRQ2
44
PA7/TCLKB//CS3
45
PA6/TCLKA//CS2
46
PA5/SCK1//DREQ1//IRQ1 T-FAULT
47
PA4/TXD1
48
PA3/RXD1
49
PA2/SCK0//DREQ0//IRQ0 FLCK
50
PA1/TXD0
www
51
PA0/RXD0
52
D15
53
D14
54
D13
.
55
VSS
56
D12
http://www.xiaoyu163.com
Name
SP_ON
T_MUTE
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
VCC
A17
VSS
DC_ON
USBSOF
USBINT
VSS
/EAINT
A18
/D_RST
/DIRINT
/AC3MUTE
VSS
RDB
/WDTOVF
/WRH
VCC
WRL
VSS
EACS
FLASHCS
/ICD
/NONPCM
SRAMCS
USBCS
TX
RX
FLDA
FLCS
D15
x
ao
u163
y
D14
D13
i
VSS
D12
http://www.xiaoyu163.com
2 9
8
I/O
Function
O
Speaker relay control (H: ON, L: OFF ) (Not used)
O
Tripath Amp Mute (Not used)
GND
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
O
Address bus
+5V
O
Address bus
GND
I
Power down detection (using power level detection)
I
Start of Frame input from USB
Q Q
3
6 7
1 3
1 5
I
Interruption input from USB
GND
I
Interruption input from Gate Array
O
Address bus
O
Reset signal for YSS928, CS5360(A/D), AD1854(D/A)
I
Interruption input from YSS928 (DIR)
I
Interruption input from YSS928 (MUTE)
GND
O
Control signal output for reading
Watched timer overflow output (Not used)
O
Control signal output for upper byte writing
+5V
O
Control signal output for lower byte writing
GND
O
Chip select output for Gate Array
O
Chip select output for external ROM
O
Chip select output for FL driver
I
Interruption input from YSS928 (NONPCM)
O
Chip select output for SRAM
O
Chip select output for USB
I
Protection for Tripath Amp (Not used)
O
Serial data output for Debug Monitor (RS232C)
I
Serial data input for Debug Monitor (RS232C)
O
Serial clock output to FL driver
O
Serial data output to FL driver
O
Chip select output to FL driver
I/O
Data bus
co
I/O
Data bus
I/O
Data bus
.
GND
I/O
Data bus
9 4
2 8
0 5
8
2 9
9 4
2 8
m
DP-U50
9 9
9 9
20