ASTRON UniBoard2 Manual - Halaman 9

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8 Default flash firmware Image

In the flash a default image, see RD-4, is installed. When the board is powered up the QSFP LED's will be

red during build in self test and start blinking green when the test is successful.

Depending on the firmware an external ID can be used for example the Ethernet IP/MAC. In Error!

Reference source not found. the location of the dip-switch is shown. This dipswitch is located at the back

side of the box.

To use JTAG, Node 3 has to be enabled, see section 9.3. In the firmware of the Lattice CPLD (U4) the JTAG

jumpers are programmed as shown in Table 6.

open

placed

open

placed

J8 and J9 must be placed to pin 1-2 for normal operation (to the backplane side of the board), by placing the

jumpers to 3-4 the CPLD (U4) can be programmed. J1 and J7 are not used by the firmware in the Lattice

device (U4). In Figure 3 the locations of the jumpers are shown.

For programming the FPGAs with the Altera USBBlaster the front and back nodes can be placed in a single

loop by placing J4 and J9 (see Table 6). In Altera's Quartus II programming utility Node 0 is placed at

location 1, Node 1 at location 2, Node 2 at location 3 and Node 3 at location 4.

UniBoard

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Table 6 JTAG jumper functions

open

Open

placed

Lat. Func.

Manual

Function

Scanbridge mode

All FPGAs in the loop

Skip node 0

Skip node 1

Skip node 2

Skip node 3

Doc.nr.:

Rev.:0.1

DESP

Date:11/05/2015

Class.:

ASTRON-IS-036 1.0