Aries Embedded RISC-V on MAX10 Panduan Pengguna - Halaman 6
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Halaman CetakRISC-V on MAX10 User Guide
The
reference designs
demonstrate the implementation of an open-source RISC-V core running FreeRTOS
and interfacing with different peripherals. This guide shows how to install the neccessacy requirements and
how to run and modify the RISC-V examples on the MX10 and SpiderBoard SoMs. The examples are also
suitable as starting point for developement.
2.1 Cores
The following open source cores are available as Intel Platform Designer (Qsys) Component:
•
Serv
The Serv core by Olof Kindgren is a bit-serial RV32I core. By only handling one bit at a
time, the core trades performance for its small size. An additional memory-mapped interrupt
controller is connected to the core to enable external, software and configurable timer inter-
rupts similar to as described in the RISC-V specification. As such the Serv is fully capable
of running FreeRTOS.
•
PicoRV
The PicoRV32 core by Claire Wolf implements the RV32I[M][C] architecture. The core
connects to the avalon-interconnect via its native memory interface. The external PCPI, look-
ahead and trace interface are not connected. The core implements its own native interrupt
controller.
•
VexRiscv
The VexRiscv core by SpinalHDL is written in Scala, highly configurable and builds to Verilog
via SpinalHDL. Five different variants were built and merged into one component to allow
specification of the supported architecture. RV32I[M] and RV32IM[A[F]C] with data and
instruction caches are available. Similar to the Serv a memory mapped interrupt controller
is implemented.
Chapter 2. Introduction
CHAPTER
TWO
INTRODUCTION
Page 6 of 20