AMD Geode LX CS5536 Manuale - Pagina 4

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3.3

Initialization Steps

Some of the following steps may be optional, depending on

the specific implementation. The reader is encouraged to

have a copy of the JEDEC standard for DDR2 SDRAM,

including the SPD byte definitions. The AMD Geode™ LX

Processors Data Book, order# 33234, is also recom-

mended. The chapters for the memory controller and

GeodeLink™ Control Processor (GLCP) register definitions

will be useful.

3.3.1

Memory Controller Initialization

Enable the CKE signal earlier, if necessary. With the

On-DIMM solution, this allows the CPLD to come out

of reset. The CPLD cannot respond to any SPD reads

while in the reset state.

Identify whether the installed DIMM(s) are DDR2. The

information in SPD[2] (i.e., SPD byte number 2) indi-

cates the fundamental memory type. If this value

equals 8, then the memory type is DDR2. A mixture of

memory types is not supported and the BIOS should

not allow this configuration.

Program the memory speed by setting the appropriate

dividers in the GLCP_SYS_RSTPLL register. This

may be decided by retrieving data from NVRAM, from

jumpers, or by calculating the best speed dynamically.

If dynamic, the BIOS should set the memory speed

slow enough to support the installed memory. The

memory's minimum cycle time is indicated in SPD[9],

which has additional bits defined beyond the DDR

specification. If more than one DIMM is installed, the

slower of the two memories should be used in calculat-

ing the memory frequency.

Note that if setting the speed dynamically, certain con-

figurations should be avoided. These are unrelated to

the memory technology installed. As is the case with

DDR, the core frequency must never be lower than the

GLIU frequency. The BIOS should try to avoid setting

an unsupported GLIU frequency.

Determine the physical configuration of the installed

DIMM(s). This procedure populates the fields in

b[63:32] of the MSR_CF07_DATA register.

SPD[5] indicates the number of ranks on the DIMM

assembly. Note that DDR2 defines this SPD byte dif-

ferently than the DDR spec. The LX processor's mem-

ory controller only supports DIMMs with 1 or 2 ranks

(indicated by 0 or 1). This setting determines the value

in the Dn_MB fields (i.e., D0_MB and D1_MB fields).

SPD[17] indicates the number of component banks.

The LX processor's memory controller only supports 2

or 4 banks, but DDR2 devices may support 4 or 8. The

Dn_CB fields should be programmed with a 1 to indi-

cate 4 banks. The BIOS should not allow configura-

tions indicating 8 banks.

Calculate the size of each DIMM. SPD[31] indicates

the density of each rank and it is defined differently

than in the DDR specification. Multiply this by the num-

ber of ranks from SPD[5] to find the DIMM size. This

value is used to program the Dn_SZ fields.

Calculate the page size (i.e. the size of each row) for

each DIMM. The page size is defined as:

(# of columns)

DIMM width * 2

SPD[4] indicates the number of column addresses.

The width should always be 8 bytes, but may also be

read from SPD[6]. The LX processor's memory con-

troller only supports memory configurations that are

64 bits wide. The size is used to program the Dn_PSZ

fields.

Calculate the CAS# Latency (CL) and Write Latency

(WL). The WL is set with the WR2DAT field of the

MC_CF1017_DATA register. This is a change from

DDR to DDR2. With DDR technology WL=1, but for

DDR2 the WL=CL-1.

As of this writing, the memory controller may only

operate at WL=1 (i.e., WR2DAT may only be pro-

grammed to equal 1). This condition forces all imple-

mentations to use a CAS# Latency of 2.

A typical CAS# Latency algorithm should use the data

in SPD[18], which is a bitmap of supported CL settings

(in units of memory clocks). The bitmap will have up to

3 bits set, representing (from most significant to least)

CL=X, CL=X-1 and CL=X-2, which is different than the

DDR definition. Additionally, SPD[9], SPD[23] and

SPD[25] will have the minimum cycle times at the

highest CAS# Latency setting, the next lower setting,

and second lower setting. Note that all cycle times

have additional bits defined in the DDR2 specification.

Normally, if two DIMMs are present, the algorithm

should set the lowest number that is supported by both

DIMMs at the current operating frequency. The pro-

cess would be identical to DDR, however, it is simpli-

fied for DDR2 memory because of the requirement to

operate at CL=2.

In the event that SPD[18] does not indicate a sup-

ported CAS# Latency of 2, the BIOS may still take

some steps to determine if CL=2 is supportable. The

fundamental CAS# access time may be calculated

using the supported CAS# Latencies and their associ-

ated cycle times. Multiplying the number of clocks by

the cycle time equals the access time. Use the lowest

result from all the supported CL values. Then divide

this number by 2 to get the lowest cycle time support-

able at CL=2. If the cycle time of the memory clock is

greater than or equal to this value, then CL=2 is typi-

AMD Geode™ LX Processor DDR2 BIOS Porting Guide

Application Note

46959A - March 2009