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Serial audio data comes out of U2 on pins 10, 16, 17, and 18. The audio master clock,

SPDIF_256FS clocks at 256 times the audio sample rate.

The analog receiver section of the CS8415A operates off the +5V supply rail and the digital/logic

sections operate off the +3.3V supply rail.

2.12 Compressed Audio Decoder

Sheet 2 of SD254175

Serial audio data and clocks from the CS8415A S/PDIF receiver are piped to the CS49329 De-

coder DSP, U103. This IC operates in one of three modes, depending on the type of data being

received. When the type of data coming in is detected, the firmware corresponding to the type of

decoding necessary is downloaded to the CS49329 from the Sharc. Once this appropriate de-

coder program is running in U103, the decoder will output the decompressed audio (or in the case

of stereo PCM, pass it through) on the lines 49300_AUDATA0-2, along with corresponding clocks

49300_64FS and 49300_LRCLK. The clock signals and 49300_AUDATA0 are buffered by U105,

since they drive multiple inputs on the Sharc.

The CS49329 (U103) is controlled and program code downloaded from the Sharc via an 8 bit

parallel bus and associated handshaking lines. U103's processor clock is derived from the clock

input node labeled "10 MHZ", which is created by the Sharc's PWM1 output. This clock actually

runs at 7.5 MHz. The CS49329 also has an onboard PLL for clock generation which utilizes R106

and C106/108 for detector output filter.

The CS29329 operates solely off the +2.5V supply rail. It also has separate analog and digital

supplies and each individual supply pin(s) are decoupled with ferrite beads and bypass capacitors.

The digital inputs and output of the CS49329 are all 3.3V-logic compatible, allowing it to interface

with the 3.3V Sharc and S/PDIF receiver.

2.13 Audio Codec

Sheet 5 of SD254175

The audio codec, U401, is a CS4428A, which has stereo A-to-D converters and six D-to-A con-

verters on it. As implemented the A-to-D converters are not used. In fact, they are powered down

using an I2C control register in the part.

The codec is controlled via an I2C interface which allows the Sharc to program the device's control

registers and read back status information from the device. The digital audio information is read

into the codec via 3 two channel serial data lines (4228_SDIN1-3) and their associated bit and

frame clocks, 49300_64FS and 49300_LRCLK, respectively. The master, 256*Fs clock in run off of

the SPDIF_256FS output from the CS8415A S/PDIF receiver IC (U2).

The circuitry hanging off the codec's analog inputs (pins 16, 17, 19, & 20) is unused in the current

application. This circuitry was intended to allow the unit to measure its own Left output channel in

order to perform self-diagnostics and calibration of the tracking power supply. The calibration of the

tracking power supply is currently performed when the unit is manufactured.

The analog inputs and outputs of the codec are internally biased and referenced around (nomi-

nally) 2.3V. This internal reference voltage is brought out at pin 18 (FILT) and bypassed to ground

by C407. Since this pin is a high impedance output, no current can be drawn from it without ad-

versely affecting the codec's performance. To match the external circuitry to the analog outputs,

Theory of Operation

PS18/28/35 Troubleshooting Guide