Chrontel CH7515A Layout Design Manual - Page 12

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CHRONTEL
U2
C1
0.1uF
DP3N
1
2
GND
ML_Lane3n
GND
3
4
DP3P
C2
0.1uF
ML_Lane3p
ML_Lane2n
GND
5
6
GND
ML_Lane2p
C4 0.1uF
7
8
DP1N
GND
ML_Lane1n
GND
9
10
DP1P
DP0N_ML
DP0N_ML
ML_Lane1p
ML_Lane0n
C6 0.1uF
GND
11
12
DP0P_ML
DP0P_ML
GND
ML_Lane0p
13
14
GND
GND
GND
GND
AUXP
15
16
GND
AUX_CHp
GND
AUXN
17
18
HPDET
HPDET
AUX_CHn
HPDET
19
20
DPPWR
RTN_DPPWR
DPPWR
R8
GND
GND
GND
GND
10K
DP_sink
22
23
24
25
GND
DP Interface
Note:
The resetb is 1.8V level. It need 10Kohm
resister to 1.8V and
0.1uf capacitor to GND.
So if the system reset signal is 3.3V,the level shift
circuit is necessary.
NOTE: CH7515/CH7516 supports three kinds of clock input ways
Option1: use 27MHz crystal with 22pf capacitors
Option 2: inject clock 14.318MHz(3.3V) in REFCK pin(Pin 10)
Option 3: inject clock 27MHz (3.3V) in REFCK pin(Pin 10)
Customer must choose one option for CH7515/CH7516 clock. We
suggest that the customers use crystal or 27Mhz clock ways
+3.3V
+12V
3
Q3
1
H2N7002
3
1
JP1
2
HEADER 3
2
U5
1
S1
R27
2
G1
50k
3
S2
R28
4
G2
50k
3
AMP4953
R29
1
BLR_EN
Q4
MMBT3904
10k
2
3
R30
BLL_EN
1
Q5
MMBT3904
10k
2
+12V
+5V
+3.3V
1 3 5
R31
J1
3
Q6
2 4 6
1
H2N7002
2
U6
1
S1
D1
R32
2
G1
D1
50k
3
S2
D2
4
G2
D2
3
AMP4953
R37
1
VDDEN
Q7
MMBT3904
10k
2
Panel Voltage and backlight control circuit
HPDET
+3.3V
HPDET
SPC0
SPC0
R21
R20
SPD0
SPD0
10k
10k
GPIO[0]
GPIO[0]
GPIO[1]
PSEL[2]
PSEL[1]
PSEL[0]
GPIO[1]
GPIO[2]
GPIO[2]
R23
R24
GPIO[3]
GPIO[3]
10k
10k
+3.3V
R1
R2
R3
6.8k
6.8k
6.8k
1
2
3
4
Boot Room
12
C5 0.1uF
DP2N
DP2P
C3 0.1uF
C7 0.1uF
DP0N
DP0P
C8 0.1uF
+3.3V
R7
49.9
VCC33
R15
10K
3
PMBS3904
1
Q1
3
2
PMBS3904
1
R19
Q2
RESETB_PCH
1k
2
C29
0.1uF
C31
22pF
Y1
27MHz
C33
R26
Backlight_R
22pF
470
8
D1
7
D1
6
Backlight_L
D2
5
D2
VCC_PanelDriver
470
8
+3.3V
7
6
R10
10K
5
SW2
PWRDN
R16
10K
C27
0.1uF
R22
10k
NOTE: PSEL[2:0]
are
for
C35
SPDIF
Spdif_out
selecting panel
1uF
R25
10k
audio(Spdif)
NOTE:
1. The dotted line parts are option funtion circuits.
+3.3V
2. The voltage circuit can only support CH7515/CH7516 chip to work.If supporting
+3.3V
the panel voltage, please add the other circuit.
R4
R6
R5
3. Whether to use PWM_IN(3.3V), PWM_OUT(3.3V)
1.8k
6.8k
6.8k
U3
is determined by customers.Which is used for Panel luminance adjustment.
8
GP1
VCC
7
4. DP and LVDS diffential pairs should be as short as possible. Please see
GP2
WE
6
SPC1
GP3
SPC
5
SPD1
GND
SPD
appliciton note for detial layout guide
CH9904(SOIC-8 package)
Figure 13: CH7515A Reference schematic
Power
Supply
4
IRU1206-18
pin
U1
Vout
Gnd
Vin
+3.3V
1
2
3
VCC33
L1
Bead
C9
C10
0.1uF
10uF
VCC33
VCC18
C22
C23
C24
C25
0.1uF
0.1uF
0.1uF
0.1uF
C13
0.1uF
VCC18
2
R11
R12
10K(1%)
10K
1
VCC18
VCC18
VCC18
DP3N
DP3P
DP2N
DP2
DP1N
DP1P DP0N
GND
GND
GND
128
127
126
125
124
123
122
121
120
119
118
117
116
115
U4
GNDBG
RBIAS
VDDBG
VDDRX
RXN3
RXP3
GNDRX
RXN
RXP2
VDDRX
RXN1
RXP1
GNDRX
RXN0
1
RB
2
Reserved
VCC18
3
VDDPLL
GND
4
GNDPLL
5
VCC18
VDDPLL
6
XO
7
XI
8
VCC18
DVDD
9
GND
DGND
REFCK
10
REFCK
11
GPIO[0]
GPIO[0]
12
GPIO[1]
GPIO[1]
13
NC
14
NC
15
NC
16
NC
17
NC
18
NC
19
NC
20
NC
21
VCC33
AVDD
GND
22
AGND
TXE3P
23
LC3P
24
TXE3N
LC3N
25
TXD3P
LD19P
TXD3N
26
LD19N
27
TXCK3P
LD18P
TXCK3N
28
LD18N
TXC3P
29
LD17P
30
TXC3N
LD17N
TXB3P
31
LD16P
TXB3N
32
LD16N
LD15P
LD15N
LD14P
LD14N
LD13P
LD13
LD12P
LD12N
LD11P
LD11N
LD10P
LD10N
LC2P
LC2N
33
34
35
36
37
38
39
40
41
42
43
44
45
46
CH7515A
TXCK2P
TXCK2
TXA3P
TXA3N
TXE2P
TXE2N
TXD2P
TXD2N
TXC2P
TXC2N
TXB2P
TXB2N
TXA2P
TXA2N
Note:It is a option that Each 100ohm resistor
should be linked in each LVDS N/P differential signals
+3.3V
+3.3V
R9
R14
R33
10K
10K
10K
SW1
SW3
BLDN
BLUP
BLUP
BLUP
BLUP
R17
R18
10K
10K
C26
C28
R38
10K
0.1uF
0.1uF
Note: GPIO[1]~GPIO[3] must be pull low
or high as input IO
MCLK
MCLK
SDATA
SDATA
Spdif_out
WS
WS
SCLK
SCLK
audio(IIS)
206-1000-021
AN-B021
+1.8V
L2
VCC18
Bead
C11
C12
10uF
0.1uF
C14
C15
C16
C17
C18
C19
C20
C21
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2
R13
100K
1
PWM_OUT
PWM_IN BLR_EN
BLL_EN
HPDET
VDDEN
VCC18
VCC18
VCC33
DP0P
BLUP
BLDN
SPC0
SPD0
SPC1
SPD1
GND
GND
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
VDDPLL
GND_PLL
PWM_OUT
BLL_EN
BLR_EN
AVSS
RXP0
VDDRX
HPDET
BLUP
BLDN
SPC0
SPD0
SPC1
SPD1
PWM_IN
AVCC
VDDEN
96
AUXP
95
AUXN
94
PSEL[2]
PSEL[2]
93
PSEL[1]
PSEL[1]
92
PSEL[0]
PSEL[0]
91
PWRDN
PWRDN
90
SCLK
SCLK
89
WS
WS
88
SDATA
SDATA/SPDIF
87
MCLK
MCLK
86
GND
DGND
85
VCC18
DVDD
84
GPIO[3]
GPIO[3]
83
GPIO[2]
GPIO[2]
82
NC
81
NC
80
NC
79
NC
78
NC
77
NC
76
NC
75
NC
74
VCC33
AVDD
73
GND
AGND
72
TXA0N
LD0N
71
TXA0P
LD0P
70
TXB0N
LD1N
69
TXB0P
LD1P
68
TXC0N
LD2N
67
TXC0P
LD2P
66
TXCK0N
LD3N
65
TXCK0P
LD3P
AGND
AVDD
LC1P
LC1N
LD9P
LD9N
LD8P
LD8N
LD7P
LD7N
LD6P
LD6N
LD5P
LD5N
LC0P
LC0N
LD4P
LD4N
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VCC33
GND
TXCK1P
TXCK1N
TXE1P
TXE1N
TXD1P
TXD1N
TXC1P
TXC1N
TXB1P
TXB1N
TXA1P
TXA1N
TXE0P
TXE0N
TXD0P
TXD0N
+3.3V
JP10
R34
R35
SPC0
1 2
10K
10K
HEADER 1x2
GPIO[3]
GPIO[2]
GPIO[1]
JP11
SPD0
1 2
HEADER 1x2
R39
R40
10K
10K
GPIO[0]
HEADER 1x2
Must be reserved, Jumper canbe
replace with 0 ohm resisitor
Rev 1.0
C30 0.1uF
AUXP
AUXN
C32 0.1uF
SPDIF
SPC1
SPD1
JP12
VDDEN
1 2
2020-07-15