Aries Embedded RISC-V on MAX10 Gebruikershandleiding - Pagina 7

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RISC-V on MAX10 User Guide

2.1.1 RISC-V Core Benchmark

The following tests were conducted on the MX10-U (with 10M50DAF256I7G, Speedgrade 7) using Quartus
20.1 Lite.
Quartus Compilation effort was set to Performance (Aggressive) with most options that increase max-
imum frequency turned on. The clock frequency of the FPGA system was 25 MHz. The benchmarks were
compiled using GCC version 11.1.0 with the compiler flags -O3

2.1.1.1 Dhrystone

Core @ 25 MHz
Serv (RV32I)
PicoRV Small (RV32I)
PicoRV (RV32IM)
VexRiscv (RV32IM)
VexRiscv+Cache (RV32IMAFC)

2.1.1.2 CoreMark

Core @ 25 MHz
Serv (RV32I)
PicoRV32 Small (RV32I)
PicoRV32 (RV32IM)
VexRiscv (RV32IM)
VexRiscv+Cache (RV32IMAFC)

2.1.2 FPGA Resource Usage

For the resource usage statistics the Quartus Compilation effort was set to Area. The data was taken from
the fitter report.
Core
Serv (RV32I)
PicoRV Small (RV32I)
PicoRV (RV32IM)
VexRiscv (RV32IM)
VexRiscv+Cache (RV32IMAFC)
Results are specific to exact compilation of the FPGA design and firmware, results may not be
Note:
reproducable.
Chapter 2. Introduction
Dhrystones/s
DMIPS
DMIPS/MHz
1262
0.718
0.028
13347
7.596
0.303
14705
8.369
0.334
48449
27.574
1.102
61950
35.258
1.410
Iterations
CoreMark
CM/MHz
10
0.590
0.024
110
6.351
0.254
200
16.577
0.663
600
50.123
2.005
1100
61.811
2.472
Logic Cells (Total)
Logic Cells (Core)
1126
383
2929
2523
3148
2766
3243
2404
9151
7537
f
DMIPS
max
max
135.8 MHz
3.938
130.3 MHz
40.263
123.9 MHz
42.250
86.8 MHz
97.824
77.3 MHz
112.626
f
CoreMark
max
max
135.8 MHz
3.123
130.3 MHz
32.705
123.9 MHz
81.774
86.8 MHz
172.298
77.3 MHz
189.076
M9K / Bits (Core)
1 / 1152
0
2 / 2340
2 / 2048
21 / 131520
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