Avnet Zynq Mini-ITX Руководство - Страница 7

Просмотреть онлайн или скачать pdf Руководство для Материнская плата Avnet Zynq Mini-ITX. Avnet Zynq Mini-ITX 11 страниц. Development board arm pjtag interface

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 As shown, the PJTAG interface I/O pins are mapped to the Zynq PL I/O pins.

Reference Design Files

 Unzip the reference design to your hard drive. The reference design zip file

contains the following folder and zip file:

o zynq_mini_itx_pjtag_design.zip

o ready_to_download

The zynq_mini_itx_pjtag_design.zip file contains the archived of the Vivado

2013.4 design that shows how to connect the ARM PJTAG port to the Zynq

Programmable Logic (PL) EMIO pins. The ready_to_download folder contains

files that are needed to boot the Zynq Mini-ITX board and enable the ARM

PJTAG connections.

 The ready_to_download folder contains the following files:

o Zynq Mini-ITX board FSBL ELF file (generated by exporting the

reference design Vivado project to SDK)

o PL bitstream to connect the PJTAG signals to the PL EMIO pins

(bitstream is generated via the Vivado project)

o U-Boot ELF file (this is a pre-build file for the Zynq Mini-ITX board)

o microSD card boot.bin image used to boot the Zynq processor (you can

re-create this image using the above 3 files in SDK, if needed)