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2.10 Bass and Satellite Clip Detect Inputs

Sheet 3, 8 of SD254175

The Power Amplifier board has circuitry to predict signal clipping of the amplifier outputs on posi-

tive going peaks. These events are separately sensed for the Bass channel and the satellite

channels (all 5 are logic-OR'd together) and brought on to the DSP board through J604. They pass

through RC lowpass filters and connect directly to the Sharc's IRQ1 and IRQ2 inputs. At this time,

these inputs have no effect on the signal processing other than briefly lighting the amber LED

whenever a satellite clip event occurs. The DSP's soft-clipper and limiter algorithms perform all of

the compression and gain limiting functions normally associated with feedback limiters. In the near

future, this circuitry will be removed from the Amp and DSP boards for cost savings.

2.11 S/PDIF Receiver

Sheet 1 of SD254175

The only audio input for the bass module is through the differential (balanced) S/PDIF input on

pins 7,8 of J1 (RJ-45 connector). The S/PDIF signal is coupled into the unit via bypass capacitors

(C609/610) to the chassis and SMD ferrite beads (FB3/4) to help alleviate EMI problems. A DC

blocking capacitor, C18, prevents DC currents from saturating the coupling transformer T1. T1 is a

broadband pulse transformer with a 1:1 turns ratio which performs the function of isolating the

incoming signal as well as balanced-to-unbalanced conversion. The secondary of T1 is connected

to a pair of back-to-back diodes that provide the "termination" for the input signal. This allows long

runs of wire and unknown transmission line impedances to exist between the head-end and bass

module and still be able to recover the S/PDIF signal. The clamped signal is fed into a resonated

LC lowpass filter which provides a sharp roll off at approximately 8 MHz. This allows S/PDIF data

at up to 48 kHz sample rate to pass through, but sharply attenuates out of band noise and tran-

sients which might cause interruptions in the S/PDIF data stream. This filtered, single-ended signal

is then fed into the RXP0 input (pin 4) of the CS8415A (U2). The RXP0 and RXN0 inputs are

internally biased to approx. 1/2Va (or approx. 2.5V). Both of these inputs are AC coupled through

capacitors.

The CS8415A (U2) recovers the serial audio data clocks by using a PLL, whose DC detector

output is filtered by the components attached to pin 8, R17 and C8/9. These audio clocks are

master for the function of the rest of the audio signal processing chain and DACs.

The CS8415A communicates setup and status information to/from the Sharc via an I2C port using

the SDA and SCL signals.

The status of the EMPHASIS bit in the S/PDIF stream is reflected on the /EMPH output, pin 3 or

U2. This line is connected to the Sharc (U4) and allows the appropriate de-emphasis to be per-

formed on signals which have pre-emphasis.

Errors and problems with the incoming S/PDIF stream are signaled to the Sharc in two ways. The

RERR output (pin 11) of the CS8415A is connected via Q8 and R219 (forming a logic inverter) to

IRQ0 of the Sharc (U4) so that problems with the audio data stream can be quickly detected and

the audio outputs muted before pops, clicks, etc. can be heard. The RERR pin is also logic-OR'd

with the output of a simple "missing-pulse detector" formed by Q7. This signal, 8415_CLKERR,

goes high when either the CS8415A has detected a problem or the LRCLK (serial audio data

frame clock) has stopped. This 8415_CLKERR signal also goes to the Sharc (U4) through the

multiplexor U601.

Theory of Operation

PS18/28/35 Troubleshooting Guide