Baumer HMG11 N29 Handbuch - Seite 14

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4.4.2.

Realtime (RT) Class 1

Typical cycle time in realtime is 100ms or better.

The bus system allows for standard Ethernet components.

Topology planning is not mandatory, but where implemented (e.g. for retrieving feature „Support device

replacement without exchangeable medium"), make sure ports P1/P2 are correctly assigned as projected.

4.4.2.1.

Address-Assignment within the Process Image

Access to the encoder's input and output data takes place via addresses within the PLC's process image.

Assign these addresses according to the needs of the PLC software.

Click on the encoder symbol in HW config of Step7 to select the encoder. Then double-click on module

"encoder data 32 bit I/O (slot 1) at left below, opening the properties window with tab "Addresses".

Enter the start address of the respective address range or accept the system's proposal. Identical or

overlapping addresses for input and output are possible. Make sure that the address ranges are located

inside the cyclically updated process image "OB1 PI" of the main program (non-isochronous).

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