ATI Audio DDA224-BNC Betriebs- und Wartungshandbuch - Seite 3
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INPUT EQUALIZERS
The input signals feed cable equalizer circuits U3 (U4) and associated
components. Input equalization should only be necessary for extremely long
input cable lengths and should only be used if proven to be necessary. The
equalizers are adjustable with front panel multi-turn trimpots R63 (R66) so that
only the minimum amount of boost required to compensate for excess cable roll-
off can be added without over-equalization, which can degrade noise margins.
See adjustment instructions in the INSTALLATION section. If input equalization
is not required and you want to protect yourself from random control diddlers, you
may disable the equalizers by removing jumpers E4 (E5).
RECEIVERS
The equalized AES/EBU data stream is applied to the receiver circuit U8 (U17)
that is a Crystal Semiconductor CS8414 96kHz Digital Audio Receiver IC. The
CS8414 receives the data, recovers the clock and synchronization signals and
separates the audio and digital data. The audio data may be 16 to 24 bits at
sample rates from 27 to 96 kHz.
Frame sync (FSYNC), Serial Clock (SCK), Serial audio data (SDATA), Channel
status (C), User channel data (U), and data validity information (VERF) are
passed directly to the transmitter IC for reformatting into the output data stream.
VERF is an OR'ing of the validity information from the incoming data (V) with an
internal error flag (ERF) that detects serious transmission errors such as parity
errors, bi-phase coding violations and an out-of-lock PLL receiver. VERF then
becomes the transmitted validity bit (V) and can be used by downstream error
correction devices to interpolate through errors.
Received frequency information is encoded on U8 (U17) pins F0, F1 and F2 and
is decoded by U14 (U19) into two BCD digits for display. Error information is
encoded on pins E0, E1 and E2. It is decoded by 3 to 8 line decoder U20 (U22)
and sent to the front panel display LEDs.
DISPLAYS
The two most significant digits of the sample rate are decoded by U1 AND U4
and displayed if the sample rate is within ±4% of a standard rate. Since only two
digits are displayed, readouts of 32, 44, 48, 88 and 96 correspond to actual
sampling rates within four percent of 32.0, 44.1, 48.0, 88.2 and 96kHz. The
displays are blanked if the detected frequency is out of range.
Data and transmission errors are displayed in priority order of No Lock, BI-
PHASE Coding errors, PARITY errors and CRC errors. The No-Lock signal is
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