Dynamic Engineering PCIe8LXMCX2CB Benutzerhandbuch - Seite 10

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XMC Module Backplane IO Interface Pin Assignment

The figure below gives the pin assignments for the XMC Module IO Interface – from Jn4
and/or Jn6 to the PCIe8LXMCX2CB connectors. Also see the User Manual for your
XMC board for more information. Please note that P2 or P13, P7 or P5 are installed not
both.
DIN IDC [P13,P5]
A1
C1
A2
C2
A3
C3
A4
C4
A5
C5
A6
C6
A7
C7
A8
C8
A9
C9
A10
C10
A11
C11
A12
C12
A13
C13
A14
C14
A15
C15
A16
C16
A17
C17
A18
C18
A19
C19
A20
C20
A21
C21
A22
C22
A23
C23
A24
C24
A25
C25
A26
C26
A27
C27
A28
C28
A29
C29
A30
C30
A31
C31
A32
C32
FIGURE 1
Read table:
P13-C1 = P2-35 = Pn4-1 P13-A1 = P2-1 = Pn4-3 etc.
With Jn6: Pins: A, B, D, E of rows 2, 4, 6, 8, 10, 12 ,14, 16, 18 are grounded
Effective connections with RIO column of resistors installed and both connector
selectors.
SCSI II [P2,P7]
Sig/Sig
1
35
0N/0P
2
36
1N/1P
3
37
2N/2P
4
38
3N/3P
5
39
4N/4P
6
40
5N/5P
7
41
6N/6P
8
42
7N/7P
9
43
8N/8P
10
44
9N/9P
11
45
10N/10P
12
46
11N/11P
13
47
12N/12P
14
48
13N/13P
15
49
14N/14P
16
50
15N/15P
17
51
16N/16P
18
52
17N/17P
19
53
18N/18P
20
54
19N/19P
21
55
20N/20P
22
56
21N/21P
23
57
22N/22P
24
58
23N/23P
25
59
24N/24P
26
60
25N/25P
27
61
26N/26P
28
62
27N/27P
29
63
28N/28P
30
64
29N/29P
31
65
30N/30P
32
66
31N/31P
33
67
Open, +3 or GND via J2,19 silk screen defined
34
68
Open, +3 or GND via J3,20
PCIE8LXMCX2CB JN4/JN6 INTERFACE STANDARD
Embedded Solutions
Jn4
3
1
4
2
7
5
8
6
11
9
12
10
15
13
16
14
19
17
20
18
23
21
24
22
27
25
28
26
31
29
32
30
35
33
36
34
39
37
40
38
43
41
44
42
47
45
48
46
51
49
52
50
55
53
56
54
59
57
60
58
63
61
64
62
Page 10
Jn6
B1
A1
E1
D1
C2
C1
F2
F1
B3
A3
E3
D3
C4
C3
F4
F3
B5
A5
E5
D5
C6
C5
F6
F5
B7
A7
E7
D7
C8
C7
F8
F7
B9
A9
E9
D9
C10
C9
F10
F9
B11
A11
E11
D11
C12
C11
F12
F11
B13
A13
E13
D13
B15
A15
E15
D15
B17
A17
E17
D17
B19
A19
E19
D19