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Fujitsu MB91460 SERIES Anwendungshinweis

INTERRUPTS

Chapter 2 Interrupt Types

2.1.3 Traps

Traps originate from within the instruction sequence. Traps are processed by first saving the

necessary information to resume processing from the next instruction in the sequence, and

then starting the processing routine corresponding to the type of trap that has occurred.

2.1.3.1 INT Instruction

"INT #u8" instruction branches to ISR indicated by interrupt vector u8. While execution of

ISR global interrupt flag is cleared (CCR:I = 0), hence all the all peripheral interrupts are

suspended until INT ISR execution has finished. However INT ISR can be interrupted by

NMI and other Traps. The System Stack Pointer is enabled (CCR:S = 0).

2.1.3.2 INTE Instruction

The INTE instruction is used to create a software trap for debugging. The INTE instruction

cannot be used in user programs involving debugging with an emulator.

2.1.3.3 Step Trace Traps

Step trace traps are traps used by debuggers. This type of trap can be created for each

individual instruction in a sequence by setting the T flag in the system condition code register

(SCR) in the program status (PS). Step trace traps cannot be used in user programs involving

debugging with an emulator.

2.1.3.4 Coprocessor Not Found

Coprocessor not found traps are generated when coprocessor instructions are executed

such as COPOP/COPLD/COPST/COPSV while the coprocessor is absent. While execution

of ISR, global interrupt flag is cleared (CCR:I = 0) hence all the all peripheral interrupts are

suspended until INT ISR execution has finished. However this ISR can be interrupted by

NMI and other Traps. The System Stack Pointer is enabled (CCR:S = 0).

2.1.3.5 Coprocessor Error

Coprocessor error trap is generated when an error has occurred in a coprocessor operation

and the CPU executes another coprocessor instruction (such as COPOP/COPLD/COPST)

involving the same coprocessor. While execution of ISR, global interrupt flag is cleared

(CCR:I = 0) hence all the all peripheral interrupts are suspended until INT ISR execution

has finished. However this ISR can be interrupted by NMI and other Traps. The System

Stack Pointer is enabled (CCR:S = 0).

2.2 Direct Memory Access (DMA)

Most of the peripheral interrupts (except few peripheral interrupt such as CAN, I2C, External

Interrupts etc.) can be used to initiate DMA transfers regardless of the status of the I flag and

the interrupt level.

For detailed information please refer to the DMA application note MCU-AN-300059.

MCU-AN-300055-E-V10

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