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2.2.2 Multiple Transfers
The following diagram shows a standard interrupt sequence and a multiple transfer DMA
sequence:
Standard Interrupt Sequence
CPU Task
Application
Peripheral Interrupt
Service Routine
Application
Peripheral Interrupt
Service Routine
Application
Peripheral Interrupt
Service Routine
Application
For a multiple transfer the DMAC advantage is obvious. During Transfer 3 and 2 the
application is not interrupted as in the standard interrupt sequence. Only after the Transfer 1,
the interrupt service routine of the DMAC is executed.
However, it should be also noted that the DMAC shares the same bus as of CPU, hence
during the time DMA is engaged in the data transfer the CPU is either waiting for the DMA to
finish the transfer or it is executing the code from the pre-fetch queue.
© Fujitsu Microelectronics Europe GmbH
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
Interrupt occurs
Interrupt occurs
Interrupt occurs
Figure 2-3: Multiple Transfers
DMA Sequence
CPU Task
Application
Application
Application
Application
End of DMA interrupts Application
Application
- 9 -
DMA Task
Interrupt occurs
DMA Transfer 3
Interrupt occurs
DMA Transfer 2
Interrupt occurs
DMA Transfer 1
DMAC Interrupt
Service Routine
MCU-AN-300059-E-V11