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Dell 3250 Produkthandbuch
Intel® Server Platform SR870BH2
Term
ACPI
Advanced Configuration and Power Interface.
ASIC
Application specific integrated circuit.
BERR
BERR Bus Error Signal. This signal can be driven by the platform to interrupt the processor that a
platform MCA condition occurred. The processor does not reset any internal state when it sees a
BERR condition. The signal causes a global MCA condition. For further information, see the
Itanium™ Processor Family Error Handling Guide.
BINIT
Bus Initialization Signal. This signal can be driven by the processor or platform to indicate a fatal
machine check condition. The processor and platform will reset internal state in order to ensure the
firmware code can be fetched and executed. This signal causes a global MCA condition. For further
information, see the Itanium™ Processor Family Error Handling Guide.
BIOS
Basic Input Output System.
BIST
Built-In Self Test.
BMC
Baseboard Management Controller.
BSP
Boot Strap Processor.
Byte
8-bit quantity.
CMCI
Corrected Machine Check Interrupt.
CMOS
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128
bytes of memory, which normally resides on the baseboard.
CPEI
Corrected Platform Event Interrupt.
DTLB
Distributed Translation Look-aside Buffer.
ECC
Error Correction Code. Refers to a memory system that has extra bit(s) to support limited
detection/correction of memory errors.
FRB
Fault Resilient Booting.
GB
1024 MB.
HSC
Hot-Swap Controller.
2
I
C
Inter-integrated circuit bus.
IERR
Internal Error.
IPMI
Intelligent Platform Management Interface. An industry standard that defines standardized,
abstracted interfaces to platform management hardware.
ISM
Intel® Server Management.
KB
Kilobyte=1024 bytes.
LAN
Local Area Network. A data communications system which allows a number of independent devices
to communicate with each other within a moderate size geographic area.
MB
Megabyte=1024 Kilobytes.
MCA
Machine Check Architecture – see SR870BH2 BIOS EPS for more detail
NVRAM
Non-Volatile RAM.
OEM
Original Equipment Manufacturer.
PAL
Processor Abstraction Layer.
PEF
Platform Event Filtering.
PERR
Parity Error. A signal on the PCI bus that indicates a parity error on the bus.
POST
Power-on Self Test.
RAM
Random Access Memory.
ROM
Read-Only Memory.
SAL
System Abstraction Layer.
SDR
Sensor Data Record.
Revision 1.1

Glossary

Definition
Glossary
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