Dell PowerEdge M910 Technisches Handbuch - Seite 25

Blättern Sie online oder laden Sie pdf Technisches Handbuch für Schalter Dell PowerEdge M910 herunter. Dell PowerEdge M910 46 Seiten. M-series blade servers
Auch für Dell PowerEdge M910: Handbuch aktualisieren (44 seiten), Handbuch aktualisieren (21 seiten), Handbuch aktualisieren (14 seiten), Installationshandbuch (7 seiten), Handbuch aktualisieren (28 seiten), Handbuch "Erste Schritte (12 seiten), Handbuch "Erste Schritte (12 seiten), Portfolio-Handbuch (27 seiten), Technisches Handbuch (45 seiten), Handbuch "Erste Schritte (14 seiten), Handbuch "Erste Schritte (12 seiten), Technisches Handbuch (49 seiten)

Dell PowerEdge M910 Technisches Handbuch
Dell
GT/s, and 6.4 GT/s with 11 Southbound lanes (9 data + 1 CRC + 1 spare) and 14 Northbound lanes (12
data + 1 CRC + 1 spare).
The DDR3 interface supports x4 and x8 single-rank, dual-rank, and quad-rank RDIMMs, and up to 2
RDIMMS per channel. Each DDR3 channel supports a maximum of 8 ranks. DDR3 speeds are 800 MT/s,
978 MT/s, 1066 MT/s, and 1333 MT/s. DRAM technology comes in 1 and 2Gb sizes. DIMM capacity is 2,
4, 8, 16, or 32 GB (16 GB with QR DIMMS only).

7.5 Memory RAS Support

The Intel Xeon processor 6500 and 7500 series supports high-availability memory modes including
rank and DIMM sparing as well as memory mirroring. The M910 supports rank sparing only and
mirroring as shown in Table 10.

Sparing

Type
Rules enforced
Rank
The capacity of the spare
rank must be greater
than that of any other
rank on the channel
7.5.1
Sparing
For information, see the
Dell PowerEdge Modular Systems Hardware Owner's Manual on Support.Dell.com.
7.5.2

Mirroring

For mirroring, the M910 will support two-processor/four-processor configurations with 32 DIMMs only.
When mirroring is enabled, only half of the physical memory will be visible to the system software. A
full copy of the memory is maintained, and in the event of an uncorrectable error, the system will
switch over to the mirrored copy. In two-processor (2P) mode, the mirroring will be inter-node with
hemisphere mode enabled. In this case, the memory controller (MBox) of CPU1 is mapped to the
corresponding MBox of CPU2.
For 4-processor (4P) configurations, the PowerEdge M910 also supports mirroring in the
inter-socket mode (intra-socket is not possible in 4P because each processor has only one MBox
connected to memory buffers). In this 4P case, the memory on CPU1 is mirrored with memory on
CPU3, while memory on CPU2 is mirrored with memory on CPU4.

7.6 Supported Memory Configurations

See the System Memory section in the Installing System Components chapter in the Dell PowerEdge
M910 Systems Hardware Owner's Manual on Support.Dell.com.
PowerEdge M910 Technical Guide
Table 10.

Sparing and Mirroring Support

Mirroring
1P
No support
System Memory
section in the Installing Blade Components chapter of the
2P
4P
Inter-socket
Inter-
(hemisphere
socket
mode
enabled)
Rules Enforced
32 DIMM only,
Mirrored must match
25