Dialog Semiconductor SLG46824 Programmierhandbuch - Seite 3

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ISPG-SLG46824/6
SLG46824/6
Introduction
This document describes the in-system programming procedures for SLG46824 and SLG46826.
1

Hardware Requirements

1.1 PINOUT AND SIGNALS

Four pins are required to program the SLG46824/6: V
The V
pin requires a voltage ranging from 2.5 V to 5.5 V for Programming (Write) operations, and 2.3 V to 5.5 V for Verification
DD
(Read) operations.
The SCL and SDA pins are defined to be standard I
Mode speed (400 kHz) NVM write communication is supported for these devices. For the timing characteristics for signals on
these pins refer to
Table
1.
, GND, SCL and SDA.
DD
2
2
C signaling. I
C Fast Mode Plus speed (1 MHz) NVM read and I
20
17
18
V
1
16
DD
19
IO0
2
15
IO1
3
14
IO2
4
13
IO3
5
12
6
IO4
11
8
9
7
10
Figure 1: STQFN-20 Pin Configuration
Revision 1.1
3 of 15
IO10
IO9
V
DD2
IO8
IO7
GND
© 2019 Dialog Semiconductor
2
C Fast
4-Mar-2019