Chrontel CH7511B Design-Handbuch - Seite 13

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CHRONTEL

GND

ML_Lane3n

GND

ML_Lane3p

ML_Lane2n

GND

ML_Lane2p

C1 0.1uF

DP1N

GND

ML_Lane1n

GND

DP1P

ML_Lane1p

ML_Lane0n

C2 0.1uF

GND

ML_Lane0p

GND

AUX P

GND

AUX _CHp

GND

AUX N

HPDET

AUX _CHn

HPDET

DPP WR

RTN_DPP WR

DPP WR

10K

DP_sink

GND

DP Interface

+3.3V

R16

R17

100

P504CT-ND

OLE D

BSS 138CT-ND

GLE D

BSS 138CT-ND

R23

R22

10k

+3.3V

10K

SW2

SW1

BLDN

BLUP

10K

C10

0.1uF

HPDET

JP10

SPC0

SPC1

SPC0

HEA DER 1x2

SPD0

JP11

SPD0

SPD1

GPIO[0]

HEA DER 1x2

GPIO[1]

GPIO[2]

JP12

IRQ

ENA VDD

GPIO[3]

HEA DER 1x2

IRQ

Must be reserved, Jumper canbe

replace with 0 ohm resisitor

+3.3V

+5V

JP1

HEA DER 3

R39

50k

R50

ENA BKL

MMB T3904

10k

+3.3V

R32

R33

R34

R35

6.8k

1.8k

GP1

VCC

GP2

GP3

SPC

GND

SPD

CH9904(SOIC-8 package)

CH7511B Boot Room

NO TE: Cu sto mer is be tte r t o l ink

sp c0 and sp d0 to SMB US/ IIC to

up dat e t he Boo t R OM lat er

206-1000-014

Rev. 1.7

Power

Supply

VCC33

C3 0.1uF

DP0N

DP0P

C4 0.1uF

VCC33

+3.3V

C12

0.1uF

VCC33

PMBS3904

R15

RES ETB_PCH

Note: The resetb is 1.8V

level.

It need 10Kohm resister to

1.8V

and

0.1uf capacitor to GND.

So if the system reset signal

is 3.3V,

the level shift circuit is

necessary.

+3.3V

NO TE: CH7511B supports two kinds of clock input ways

10K

Option1: use 27MHz cryst al with 22pf capacitors

SW3

Option 2: inject clock 27MHz (3.3V) in REFCK pin(Pin 9)

PWRDN

Customer must choose one option f or CH7511 clock

10K

C11

0.1uF

R28

PWM_OUT0

PWM_OUT1

HPDET

R29

SPC0

NO TE: PW M_O UT0 (0~ 100 % d uty cy cle or PW M b ypa ss

SPD0

mo de)

PW M_O UT1 (30 ~10 0% dut y c ycl e)

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

IRQ

R37

Backlight

470

H2N7002

SI4953

+3.3V

R38

R36

R18

R19

R20

6.8k

10K

GPIO[0]

SPC1

SPD1

GPIO[1]

GPIO[2]

GPIO[3]

R24

R25

R26

100

Figure 13: CH7511B/7512B Reference schematic

2020-07-14

IRU1206-18

+3.3V

+1.8V

Bead

0.1uF

10uF

0.1uF

VCC18

C13

C14

C15

C16

C17

C18

C19

0.1uF

VCC18

R12

10K

R11

10K

PMBS3904

R13

10K (1%)

C23

0.1uF

C24

RES ETB

Reserved

VCC18

22pF

AVDD

VCC18

AVDD

27MHz

VCC18

DVDD

GND

C26

GND

REFCK

CLK 2P

LL2CP

CLK 2M

LL2CN

A7P

22pF

LDC7P

A7M

LDC7N

A6P

LDC6P

A6M

LDC6N

A5P

LDC5P

A5M

LDC5N

PWM_OUT

A0M

PWM_OUT

A1M

A2M

CLK 1M

A3M

+3.3V

+5V

H2N7002

JP2

HEA DER 3

R57

50k

R58

ENA VDD

MMB T3904

10k

Panel Voltage and backl ight control circuit

NOT E:

1. T he dotted line parts are option funtion circui ts.

R21

2. T he voltage ci rcuit can only support CH7511B chip

10K

to work.If supporti ng the panel voltage, please add the

NO TE: Cu sto mer ca n c hoo se

di ffe ren t p ane l b y p ull

other circui t.

hi gh or low of GP IO[ 0:3 ].

3. Whether to use PWM_IN(3.3V), PWM_OUT 0(3.3V)

and PWM_OUT 1(3.3V) is determi ned by customers.

R27

Which is used for Panel l uminance adjustment.

100

4. DP and LVDS diffential pai rs should be as short as

possibl e. Please see applici ton note for detial layout guide

5. T he CH7511B thermal exposed pad must be linked to

GND

AN-B014

VCC18

GND

+3.3V

C20

C21

C22

0.1uF

R10

6.8k

R14

100K

SPC1

SPD1

PWM_IN

PWM_OUT0

ENA VDD

ENA BKL

GND

AUX P

CH7511B

AUX N

VCC18

DVDD

PWRDN

GND

PWM_OUT1

GPIO[3]

GPIO[2]

IRQ

GND

NO TE: If th e s ouc e o f A UX has

0. 1uF ca p, ple ase do n't ad d

ca p i n C H75 11 por t. For AU X C H

Ci rcu it, Pl eas e r efe r t o A N

an d D P S pec

A0P

A4M

A4P

R40

R41

100

A1P

A5M

A5P

R42

R43

100

A2P

A6M

A6P

R48

R49

100

CLK 1P

A7M

A7P

R51

R52

100

A3P

CLK 2M

CLK 2P

R53

R54

100

Solder option

R56

VCC PanelDriver

470

SI4953

PWM_IN

C25 0.1uF

AUX P

AUX N

C27 0.1uF