Toshiba TLP510E Technisches Schulungshandbuch - Seite 32

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7-3. Video Demodulation Block

7-3-1. Y/C Separation Circuit
This circuit separates Y and C signals from a composite
video signal. Fig. 7-3-1 shows the pin configuration of
TC9090AN and Fig. 7-3-2 shows the block diagram.
The composite video signal enters pin 3. A fsc (3.58/
4.43 MHz) developed from the video/color IC enters pin
19 and is converted into a 4fsc of the drive clock
frequency inside the IC. The composite video signal
entered is processed at a rate of the clock frequency of
the IC and output as Y and C signal.
V
1
REFH
V
2
SS1
ADIN
3
V
4
DD1
V
5
REFL
BIAS1
6
P/S
7
SDA
8
SCL
9
RESET
10
TEST1
11
TEST2
12
KILLER
13
PLLSEL
14
Fig. 7-3-1 Pin configuration of TC9090AN
Composite
2
video signal
19
Clock
28
V
SS4
27
V
DD4
V
26
REF1
25
Y
OUT
24
BIAS2
C
23
OUT
22
BIAS3
21
2/1V
DD
20
VFIL
19
CKIN
18
V
DD2
17
V
SS2
16
V
SS3
15
V
DD3
LINE
VERTICAL EDGE
ADC
MEMORY
ENHANCE CIRCUIT
8 bits
CLAMP
4.43 MHz NTSC
BPF
DYNAMIC
BPF
COMB
FILTER
BPF
PLL
4 FSC
Fig. 7-3-2 Block diagram of TC9090AN
Table 7-3-1 Terminal function of TC9090AN
Pin
Name
No.
1
V
REFH
2
V
SS1
3
ADIN
4
V
DD1
5
V
REFL
6
BIAS1
7
P/S
8
SDA
9
SCL
10
RESET
11
TEST1
12
TEST2
13
KILLER
14
PLLSEL
15
V
DD3
16
V
SS3
17
V
SS2
18
V
DD2
19
CKIN
20
VFIL
21
2/1 V
DD
22
BIAS3
23
C
OUT
24
BIAS2
25
Y
OUT
26
V
REF1
27
V
DD4
28
V
SS4
CORING
CIRCUIT
PEDESTAL
+
+
COLOR KILLER CIRCUIT
BPF
1 LINE DOT
IMPROVE
BPF
CIRCUIT
2
I
C BUS
8
9
Bus
7-5
Function
ADC bias
ADC GND
Video input
ADC VDD
ADC bias
ADC bias
Selection function control
2
I
C bus clock input
2
I
C bus data input, check output
2
I
C bus reset
est terminal
T
Test terminal
Clock killer switch
Selection input clock
Digital VDD
Analog GND
PLL GND
PLL VDD
Clock input
VCO filter
Line memory bias
DAC bias
C output
DAC bias
Y output
DAC bias
DAC VDD
DAC GND
Y
25
YDAC
output
CLIP
8 bits
C
CDAC
23
output
8 bits