Cypress S6J3200 Series Manuallines

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FPD-Link PCB Guidelines for the Traveo Family S6J3200 Series MCUs
AN211139 provides guidelines for PCB layout for the flat panel display link interface (FPD-Link) for Cypress's
Traveo™ Family S6J3200 Series MCUs.
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Introduction
Traveo Family S6J3200 Series MCUs have a flat panel display link interface (FPD-Link, with TxCLK± and
TxDOUT[0:3]±), used to connect high-performance video displays. FPD-Link is a high-speed interface (max
350 Mbps/lane) using low-voltage differential signaling (LVDS).
The FPD-Link graphics display port of S6J3200 Series MCUs has the following characteristics:
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High speed: Data rates up to 350 Mbps per lane
▪
Low voltage swing: Approximately 350 mV
▪
Five differential signals: TxCLK± and TxDOUT[0:3]±
Because of these characteristics, the PCB for FPD-Link cannot be treated as a simple group of traces. This
application note provides guidelines for the layout of the FPD-Link PCB for S6J3200 Series devices.
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Recommended PCB Specifications
The following best practices are recommended for routing the LVDS signals used in an FPD-Link interface:
▪
Use balanced transmission lines with a characteristic impedance of 100 Ω ±10%.
▪
Avoid vias by using the programmable inversion and output signal selection
▪
Ensure that the PCB design conforms to the parameters listed in
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S6J3200 Series MCUs can select the output signal for FPD-Link. Refer to Chapter 30 in the
www.cypress.com
Associated Part Family:
Related Documents: For a complete list,
Document No. 002-11139 Rev. *A
Author: Hiroo Mizuno
Traveo Family S6J3200 Series
Related Application Notes:
[1]
abilities of the FPD-Link Controller.
Table
1.
Hardware Manual
AN211139
AN213250
click here.
for more details.
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