Cypress Semiconductor CY62147DV18 Spezifikationsblatt - Seite 2
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Pin Configuration
Notes:
2.
NC pins are not internally connected on the die.
3.
DNU pins have to be left floating or tied to Vss to ensure proper application.
4.
Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
Document #: 38-05343 Rev. *B
FBGA (Top View)
1
2
4
5
3
A
A
A
OE
BLE
2
0
1
A
A
I/O
BHE
CE
3
4
8
A
A
I/O
I/O
I/O
5
6
9
10
1
A
V
I/O
A
I/O
SS
7
11
3
17
DNU
A
V
I/O
I/O
CC
16
12
4
A
I/O
A
I/O
I/O
14
15
13
5
14
A
A
I/O
NC
WE
13
15
12
A
A
A
A
NC
10
9
11
8
CY62147DV18
6
NC
A
I/O
B
0
C
I/O
2
Vcc
D
Vss
E
F
I/O
6
G
I/O
7
NC
H
MoBL2™
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