Cypress Semiconductor CY7C037AV Spezifikationsblatt - Seite 4
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Pin Definitions
Left Port
CE
, CE
CE
0L
1L
R/W
R/W
L
OE
OE
L
A
–A
A
0L
15L
0R
I/O
–I/O
I/O
0L
17L
SEM
SEM
L
UB
UB
L
LB
LB
L
INT
INT
L
BUSY
BUSY
L
M/S
V
CC
GND
NC
Architecture
The
CY7C027V/027VN/027AV/028V
CY7037V/037AV/038V consist of an array of 32K and 64K words
of 16 and 18 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communication. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave (BUSY pins
are inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output enable
control (OE), which allows data to be read from the device.
Functional Description
The
CY7C027V/027VN/027AV/028V
CY7037V/037AV/038V are low power CMOS 32K, 64K x 16/18
dual-port static RAMs. Various arbitration schemes are included
on the devices to handle situations when multiple processors
access the same piece of data. Two ports are provided, permit-
ting independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
stand-alone 16/18-bit dual-port static RAMs or multiple devices
can be combined to function as a 32/36-bit or wider master/slave
dual-port static RAM. An M/S pin is provided for implementing
32/36-bit or wider memory applications without the need for sep-
arate master and slave devices or additional discrete logic. Ap-
plication areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port video/graphics
memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are provided
on each port (BUSY and INT). BUSY signals that the port is trying to
access the same location currently being accessed by the other port.
The interrupt flag (INT) permits communication between ports or
Document #: 38-06078 Rev. *B
Right Port
, CE
Chip Enable (CE is LOW when CE
0R
1R
Read/Write Enable
R
Output Enable
R
–A
Address (A
15R
–I/O
Data Bus Input/Output (I/O
0R
17R
Semaphore Enable
R
Upper Byte Select (I/O
R
Lower Byte Select (I/O
R
Interrupt Flag
R
Busy Flag
R
Master or Slave Select
Power
Ground
No Connect
CY7C027V/027VN/027AV/028V
Description
0
–A
for 32K; A
–A
for 64K devices)
0
14
0
15
–I/O
for x16 devices; I/O
0
15
–I/O
for x16 devices; I/O
8
15
–I/O
for x16 devices; I/O
0
7
systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight shared
and
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on each port
by a chip select (CE) pin.
The
CY7C027V/027VN/027AV/028V
CY7037V/037AV/038V are available in 100-pin Thin Quad Plas-
tic Flatpacks (TQFP).
Write Operation
Data must be set up for a duration of t
R/W to guarantee a valid write. A write operation is controlled by either
the R/W pin (see
Figure
for non-contention operations are summarized in
If a location is being written to by one port and the opposite port
and
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
the user wishes to access a semaphore flag, then the SEM pin must be
asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/027VN/027AV/37V, FFFF for the CY7C028V/38V) is
the mailbox for the right port and the second-highest memory
location (7FFE for the CY7C027V/027VN/027AV/037V/037AV,
FFFE for the CY7C028V/38V) is the mailbox for the left port.
When one port writes to the other port's mailbox, an interrupt is
CY7C037V/037AV/038V
≤ V
≥ V
and CE
)
IL
1
IH
–I/O
for x18)
0
17
–I/O
for x18 devices)
9
17
–I/O
for x18 devices)
0
8
before the rising edge of
SD
7) or the CE pin (see
Figure
8). Required inputs
Table
1.
after CE or t
after OE is asserted. If
ACE
DOE
and
after
DDD
Page 4 of 18
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