Cypress Semiconductor CY7C107BN Spezifikationsblatt - Seite 3

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AC Test Loads and Waveforms
R1 480Ω
5V
OUTPUT
R2
30 pF
255Ω
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
THÉ VENIN EQUIVALENT
167Ω
OUTPUT

Switching Characteristics

Parameter
READ CYCLE
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
CE LOW to Low Z
LZCE
t
CE HIGH to High Z
HZCE
t
CE LOW to Power-Up
PU
t
CE HIGH to Power-Down
PD
[8]
WRITE CYCLE
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Set-Up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-Up to Write Start
SA
t
WE Pulse Width
PWE
t
Data Set-Up to Write End
SD
t
Data Hold from Write End
HD
t
WE HIGH to Low Z
LZWE
t
WE LOW to High Z
HZWE
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
OL
OH
6. At any given temperature and voltage condition, t
7. t
and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZCE
HZWE
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 001-06426 Rev. **
R1 480Ω
5V
OUTPUT
R2
5 pF
255Ω
INCLUDING
JIG AND
SCOPE
(b)
1.73V
[5]
Over the Operating Range
Description
[6]
[6, 7]
[6]
[6, 7]
is less than t
and t
HZCE
LZCE
3.0V
10%
GND
≤ 3 ns
7C107BN-15
7C1007BN-15
Min.
15
3
3
0
15
12
12
0
0
12
8
0
3
is less than t
for any given device.
HZWE
LZWE
CY7C107BN
CY7C1007BN
ALL INPUT PULSES
90%
90%
10%
≤ 3 ns
Max.
Unit
ns
15
ns
ns
15
ns
ns
7
ns
ns
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
Page 3 of 7
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