Cypress Semiconductor CY7C1231H Spezifikationsblatt - Seite 8

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Switching Characteristics

Parameter
t
V
(Typical) to the first Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid after CLK Rise
CDV
t
Data Output Hold after CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
OE LOW to Output Valid
t
OEV
OE LOW to Output Low-Z
t
OELZ
OE HIGH to Output High-Z
t
OEHZ
Set-up Times
t
Address Set-up before CLK Rise
AS
ADV/LD Set-up before CLK Rise
t
ALS
WE, BW
t
WES
t
CEN Set-up before CLK Rise
CENS
t
Data Input Set-up before CLK Rise
DS
t
Chip Enable Set-up before CLK Rise
CES
Hold Times
t
Address Hold after CLK Rise
AH
ADV/LD Hold after CLK Rise
t
ALH
WE, BW
t
WEH
CEN Hold after CLK Rise
t
CENH
t
Data Input Hold after CLK Rise
DH
t
Chip Enable Hold after CLK Rise
CEH
Notes:
12. Timing reference level is 1.5V when V
13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14. This part has a voltage regulator internally; t
can be initiated.
15. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
16. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 001-00207 Rev. *B
Over the Operating Range
Description
[14]
[15, 16, 17]
[15, 16, 17]
[15, 16, 17]
[15, 16, 17]
Set-up before CLK Rise
[A:B]
Hold after CLK Rise
[A:B]
= 3.3V and 1.25V when V
DDQ
DDQ
is the time that the power needs to be supplied above V
POWER
is less than t
and t
OEHZ
OELZ
CHZ
[12, 13]
= 2.5V.
minimum initially before a read or write operation
DD
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1231H
-133
Min.
Max.
1
7.5
2.5
2.5
6.5
2.0
0
3.5
3.5
0
3.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Page 8 of 12
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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