Cypress Semiconductor CY7C1306BV25 Spezifikationsblatt - Seite 4
Blättern Sie online oder laden Sie pdf Spezifikationsblatt für Computer Hardware Cypress Semiconductor CY7C1306BV25 herunter. Cypress Semiconductor CY7C1306BV25 20 Seiten. Cypress 18-mbit burst of 2 pipelined sram with qdr architecture specification sheet
Seite drucken
Pin Definitions
Name
I/O
D
Input-
[x:0]
Synchronous
WPS
Input-
Synchronous
BWS
, BWS
,
Input-
0
1
BWS
, BWS
Synchronous
2
3
A
Input-
Synchronous
Q
Outputs-
[x:0]
Synchronous
RPS
Input-
Synchronous
C
Input-Clock
C
Input-Clock
K
Input-Clock
K
Input-Clock
ZQ
Input
TDO
Output
TCK
Input
TDI
Input
TMS
Input
Document #: 38-05627 Rev. *A
Data input signals, sampled on the rising edge of K and K clocks during valid write opera-
tions.
CY7C1303BV25 – D
[17:0]
CY7C1306BV25 – D
[35:0]
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D
to be ignored.
[x:0]
Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations.
CY7C1303BV25 - BWS
controls D
0
CY7C1306BV25 - BWS
controls D
0
controls D
[35:27]
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the corresponding
byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active Read operations and
on the rising edge of K for Write operations. These address inputs are multiplexed for both Read
and Write operations. Internally, the device is organized as 1M x 18 (2 arrays each of 512K x 18)
for CY7C1303BV25 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1306BV25. Therefore,
only 19 address inputs are needed to access the entire memory array of CY7C1303BV25 and
18 address inputs for CY7C1306BV25. These inputs are ignored when the appropriate port is
deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K when in single clock mode. When the Read port is deselected, Q
three-stated.
CY7C1303BV25 - Q
[17:0]
CY7C1306BV25 - Q
[35:0]
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the K clock. Each read access consists of a burst
of two sequential 18-bit or 36-bit transfers.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive
out data through Q
when in single clock mode.
[x:0]
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q
output impedance are set to 0.2 x RQ, where RQ is a resistor
[x:0]
connected between ZQ and ground. Alternately, this pin can be connected directly to V
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Description
and BWS
controls D
[8:0]
1
[17:9].
, BWS
controls D
, BWS
[8:0]
1
[17:9]
when in single clock mode. All accesses are initiated
[x:0]
CY7C1303BV25
CY7C1306BV25
controls D
and BWS
2
[26:18]
3
are automatically
[x:0]
, which
DDQ
Page 4 of 19
[+] Feedback