Cypress Semiconductor CY7C1338G Spezifikationsblatt - Seite 11
Blättern Sie online oder laden Sie pdf Spezifikationsblatt für Computer Hardware Cypress Semiconductor CY7C1338G herunter. Cypress Semiconductor CY7C1338G 18 Seiten. Cypress 4-mbit (128k x 32) flow-through sync sram specification sheet
Seite druckenTiming Diagrams
[17]
Read Cycle Timing
CLK
t ADS
ADSP
ADSC
t AS
A1
ADDRESS
GW, BWE,BW
[A:D]
t CES
CE
ADV
OE
Data Out (Q)
High-Z
Note:
17. On this diagram, when CE is LOW: CE
Document #: 38-05521 Rev. *D
t CYC
t CL
t
CH
t ADH
t ADS
t ADH
t AH
A2
t
t
WES
WEH
t CEH
t
ADVS
t OEV
t OELZ
t OEHZ
t CLZ
Q(A2)
Q(A1)
t CDV
Single READ
is LOW, CE
is HIGH and CE
1
2
t
ADVH
ADV suspends burst.
t CDV
t DOH
Q(A2 + 1)
Q(A2 + 2)
BURST
READ
DON'T CARE
UNDEFINED
is LOW. When CE is HIGH: CE
3
CY7C1338G
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Burst wraps around
to its initial state
is HIGH or CE
is LOW or CE
is HIGH.
1
2
3
Deselect Cycle
t CHZ
Q(A2 + 2)
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