Cypress Semiconductor CY7C1338G Spezifikationsblatt - Seite 14

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Timing Diagrams
(continued)
[21, 22]
ZZ Mode Timing
CLK
ZZ
I
SUPPLY
ALL INPUTS
(except ZZ)
Outputs (Q)
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05521 Rev. *D
t ZZ
t ZZI
I DDZZ
DON'T CARE
t RZZI
DESELECT or READ Only
High-Z
CY7C1338G
t ZZREC
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