Cypress Semiconductor CY7C1338G Spezifikationsblatt - Seite 5

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Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW
controls DQ
A
BWC controls DQ
, and BW
C
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
written into the specified address location. Byte writes are
allowed. During byte writes, BW
DQ
, BW
controls DQ
, and BW
B
C
C
tri-stated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1338G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ active to sleep current
ZZI
t
ZZ Inactive to exit sleep current
RZZI
Document #: 38-05521 Rev. *D
, CE
, CE
are all asserted
1
2
3
])are ignored during this first
A:D
and BWB controls DQ
A
controls DQ
. All I/Os are
D
D
, CE
, and CE
are all asserted
1
2
3
will be
[A:D]
controls DQ
, BW
controls
A
A
B
controls DQ
. All I/Os are
D
D
Description
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation "sleep" mode. Two
clock cycles are required to enter into or exit from this "sleep"
.
B
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the "sleep" mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the "sleep" mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
LOW.
Interleaved Burst Address Table
(MODE = Floating or V
First
)
Address
[A:D]
A1, A0
00
01
10
11
Linear Burst Address Table (MODE = GND)
First
Address
A
, A
1
0
00
01
10
11
Test Conditions
ZZ > V
– 0.2V
DD
ZZ > V
– 0.2V
DD
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
CY7C1338G
after the ZZ input returns
ZZREC
)
DD
Second
Third
Address
Address
A1, A0
A1, A0
01
10
00
11
11
00
10
01
Second
Third
Address
Address
A
, A
A
, A
1
0
1
0
01
10
10
11
11
00
00
01
Min.
Max.
40
2t
CYC
2t
CYC
2t
CYC
0
Fourth
Address
A1, A0
11
10
01
00
Fourth
Address
A
, A
1
0
11
00
01
10
Unit
mA
ns
ns
ns
ns
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