Cypress Semiconductor CY7C1339G Spezifikationsblatt - Seite 6

Blättern Sie online oder laden Sie pdf Spezifikationsblatt für Computer Hardware Cypress Semiconductor CY7C1339G herunter. Cypress Semiconductor CY7C1339G 18 Seiten. Cypress 4-mbit (128k x 32) pipelined sync sram specification sheet

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Cypress Semiconductor CY7C1339G Spezifikationsblatt
[2, 3, 4, 5, 6, 7]
Truth Table
Operation
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Notes:
2. X = "Don't Care." H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
(BW
, BW
, BW
, BW
), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
, CE
, and CE
are available only in the TQFP package. BGA package has only 2 chip selects CE
1
2
3
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05520 Rev. *F
Add. Used CE
CE
CE
1
2
None
H
X
X
None
L
L
X
None
L
X
H
None
L
L
X
None
L
X
H
None
X
X
X
External
L
H
L
External
L
H
L
External
L
H
L
External
L
H
L
External
L
H
L
Next
X
X
X
Next
X
X
X
Next
H
X
X
Next
H
X
X
Next
X
X
X
Next
H
X
X
Current
X
X
X
Current
X
X
X
Current
H
X
X
Current
H
X
X
Current
X
X
X
Current
H
X
X
, BW
, BW
A
B
ADSP
ADSC
ADV WRITE OE CLK
ZZ
3
L
X
L
X
L
L
X
X
L
L
X
X
L
H
L
X
L
H
L
X
H
X
X
X
L
L
X
X
L
L
X
X
L
H
L
X
L
H
L
X
L
H
L
X
L
H
H
L
L
H
H
L
L
X
H
L
L
X
H
L
L
H
H
L
L
X
H
L
L
H
H
H
L
H
H
H
L
X
H
H
L
X
H
H
L
H
H
H
L
X
H
H
, BW
) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
C
D
and CE
1
[A: D]
CY7C1339G
DQ
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
X
Tri-State
X
L
L-H
X
H
L-H
Tri-State
L
X
L-H
H
L
L-H
H
H
L-H
Tri-State
H
L
L-H
H
H
L-H
Tri-State
H
L
L-H
H
H
L-H
Tri-State
L
X
L-H
L
X
L-H
H
L
L-H
H
H
L-H
Tri-State
H
L
L-H
H
H
L-H
Tri-State
L
X
L-H
L
X
L-H
.
2
. Writes may occur only on subsequent clocks
Page 6 of 18
Q
D
Q
Q
Q
D
D
Q
Q
D
D
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