Cypress Semiconductor CY7C1364C Spezifikationsblatt - Seite 11

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Switching Characteristics

Parameter
t
V
(Typical) to the First Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid after CLK Rise
CO
t
Data Output Hold after CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Set-up Times
t
Address Set-up before CLK Rise
AS
t
ADSC, ADSP Set-up before CLK Rise
ADS
t
ADV Set-up before CLK Rise
ADVS
t
GW, BWE, BW
WES
t
Data Input Set-up before CLK Rise
DS
t
Chip Enable Set-up before CLK Rise
CES
Hold Times
t
Address Hold after CLK Rise
AH
t
ADSP, ADSC Hold after CLK Rise
ADH
t
ADV Hold after CLK Rise
ADVH
t
GW, BWE, BW
WEH
t
Data Input Hold after CLK Rise
DH
t
Chip Enable Hold after CLK Rise
CEH
Notes:
12. Timing reference level is 1.5V when V
13. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
14. This part has a voltage regulator internally; t
can be initiated.
15. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
16. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 38-05689 Rev. *E
Over the Operating Range
Description
[14]
[15, 16, 17]
[15, 16, 17]
[15, 16, 17]
[15, 16, 17]
Set-up before CLK Rise
[A:D]
Hold after CLK Rise
[A:D]
= 3.3V and is 1.25V when V
DDQ
DDQ
is the time that the power needs to be supplied above V
POWER
is less than t
and t
is less than t
OEHZ
OELZ
CHZ
[12,13]
–250
–200
Min.
Max.
Min.
1
1
4.0
5.0
1.8
2.0
1.8
2.0
2.8
1.25
1.25
1.25
1.25
1.25
2.8
1.25
2.8
0
0
2.8
1.25
1.5
1.25
1.5
1.25
1.5
1.25
1.5
1.25
1.5
1.25
1.5
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
= 2.5V.
minimum initially before a Read or Write operation
DD
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1364C
–166
Max.
Min.
Max.
Unit
1
6.0
2.4
2.4
3.0
3.5
1.25
1.25
3.0
1.25
3.5
3.0
3.5
0
3.0
3.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Page 11 of 18
ms
ns
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ns
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