Cypress Semiconductor CY7C1365C Spezifikationsblatt - Seite 14
Blättern Sie online oder laden Sie pdf Spezifikationsblatt für Computer Hardware Cypress Semiconductor CY7C1365C herunter. Cypress Semiconductor CY7C1365C 19 Seiten. Cypress 9-mbit (256k x 32) flow-through sync sram specification sheet
Seite druckenTiming Diagrams
(continued)
[18, 19]
Write Cycle Timing
CLK
t
CH
t ADS
t ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
Byte write signals are ignored for first cycle when
ADSP initiates burst.
BWE,
BW
[A:D]
GW
t CES
t CEH
CE
ADV
OE
Data in (D)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Notes:
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
Document #: 38-05690 Rev. *E
t CYC
t
CL
t ADS
t ADH
A2
t
t
DS
DH
D(A2)
D(A1)
Single WRITE
DON'T CARE
ADSC extends burst.
t
t
WEH
WES
ADV suspends burst.
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
BURST WRITE
UNDEFINED
CY7C1365C
t ADS
t ADH
A3
t WES
t WEH
t ADVS
t ADVH
D(A3)
D(A3 + 1)
D(A3 + 2)
Extended BURST WRITE
Page 14 of 18
[+] Feedback