Cypress Semiconductor CY7C1365C Spezifikationsblatt - Seite 18

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Document History Page
Document Title: CY7C1365C 9-Mbit (256K x 32) Flow-Through Sync SRAM
Document Number: 38-05690
REV.
ECN NO. Issue Date
**
286269
See ECN
*A
320834
See ECN
*B
377095
See ECN
*C
408725
See ECN
*D
429278
See ECN
*E
501828
See ECN
Document #: 38-05690 Rev. *E
Orig. of
Change
PCI
New data sheet
PCI
Added 133 MHz in the Ordering Information table
Changed Θ
and Θ
JA
6.13 °C/W respectively
Modified V
V
OL,
OH
Corrected IDD, tCDV, tCH, tDOH and tCL for 100MHz to 180 mA, 8.5 ns, 4
ns, 2 ns and 4 ns respectively
Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics and truth
table on page# 6
Added Industrial operating range
Updated Ordering Information Table
PCI
Changed I
from 30 to 40 mA
SB2
Modified test condition in note# 9 from V
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
"3901 North First Street" to "198 Champion Court"
Changed three state to tri-state
Converted from Preliminary to Final
Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the ordering information
NXR
Added 2.5VI/O option
Updated Ordering Information Table
VKN
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
Description of Change
for TQFP Package from 25 and 9 °C/W to 29.41 and
JC
test conditions
< V
IH
DD
CY7C1365C
< V
to V
IH
DD
Relative to GND
DDQ
Page 18 of 18
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