Cypress Semiconductor Perform CY62167E MoBL Handbuch

Blättern Sie online oder laden Sie pdf Handbuch für Computer Hardware Cypress Semiconductor Perform CY62167E MoBL herunter. Cypress Semiconductor Perform CY62167E MoBL 13 Seiten. 16-mbit (1m x 16 / 2m x 8) static ram

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Features
• Configurable as 1M x 16 or as 2M x 8 SRAM
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra low standby power
— Typical standby current: 1.5 µA
— Maximum standby current: 12 µA
• Ultra low active power
— Typical active current: 2.2 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in 48-pin TSOP I package
Functional Description
The CY62167E is a high performance CMOS static RAM
organized as 1M words by 16 bits/2M words by 8 bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life™
®
(MoBL
) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
reduces power consumption by 99% when addresses are not
toggling. Place the device into standby mode when deselected
Logic Block Diagram
POWER DOWN
CIRCUIT
Note
1. For best practice recommendations, refer to the Cypress application note
Cypress Semiconductor Corporation
Document #: 001-15607 Rev. *A
16-Mbit (1M x 16 / 2M x 8) Static RAM
, CE
, and OE features
1
2
[1]
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
1M × 16 / 2M x 8
A
5
RAM ARRAY
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
CE
2
CE
1
BHE
BLE
•
198 Champion Court
(CE
HIGH, or CE
LOW, or both BHE and BLE are HIGH).
1
2
The input and output pins (IO
high impedance state when:
• The device is deselected (CE
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
• A write operation is in progress (CE
WE LOW)
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
written into the location specified on the address pins (A
through A
). If Byte High Enable (BHE) is LOW, then data
19
from the IO pins (IO
through IO
8
specified on the address pins (A
To read from the device, take Chip Enables (CE
CE
HIGH) and Output Enable (OE) LOW while forcing the
2
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on IO
to IO
0
then data from memory appears on IO
Table" on page 10
for a complete description of read and write
modes.
AN1064, SRAM System
Guidelines.
,
•
San Jose
CA 95134-1709
CY62167E MoBL
through IO
) are placed in a
0
15
HIGH or CE
LOW)
1
2
LOW, CE
HIGH, and
1
2
LOW and CE
1
through IO
0
) is written into the location
15
through A
).
0
19
LOW and
1
. If Byte High Enable (BHE) is LOW,
7
to IO
. See the
8
15
IO
–IO
0
7
IO
–IO
8
15
BYTE
BHE
WE
CE
CE
OE
BLE
•
408-943-2600
Revised June 07, 2007
®
2
), is
7
0
"Truth
2
1
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