Cypress Semiconductor Perform CY7C136 Handbuch - Seite 8
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Seite druckenSwitching Waveforms
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
ADDRESS
R
R/W
R
D
INR
ADDRESS
L
BUSY
L
DOUT
L
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port)
ADDRESS
CE
R/W
DATA
IN
OE
D
OUT
Note
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
and for data to be placed on the bus for the required t
Document #: 38-06031 Rev. *E
(continued)
ADDRESS MATCH
t
PS
t
BLA
t
SCE
t
AW
t
SA
t
HZOE
.
SD
CY7C136A, CY7C142, CY7C146
t
RC
t
PWE
VALID
ADDRESS MATCH
t
DDD
t
WDD
t
WC
t
PWE
t
SD
DATA VALID
HIGH IMPEDANCE
or t
+ t
PWE
HZWE
SD
CY7C132, CY7C136
t
BHA
t
BDD
VALID
[12, 20]
t
HA
t
HD
to allow the data I/O pins to enter high impedance
Page 8 of 15
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