Cypress Semiconductor STK11C68-5 Spezifikationsblatt - Seite 7
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AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Alt
Parameter
t
t
Chip Enable Access Time
ACE
ELQV
[4]
t
Read Cycle Time
t
AVAV,
RC
t
ELEH
[5]
t
Address Access Time
t
AVQV
AA
t
t
Output Enable to Data Valid
DOE
GLQV
[5]
t
Output Hold After Address Change
t
AXQX
OHA
[6]
t
Chip Enable to Output Active
t
ELQX
LZCE
[6]
t
Chip Disable to Output Inactive
t
EHQZ
HZCE
[6]
t
Output Enable to Output Active
t
GLQX
LZOE
[6]
t
Output Disable to Output Inactive
t
GHQZ
HZOE
[3]
t
Chip Enable to Power Active
t
ELICCH
PU
[3]
t
Chip Disable to Power Standby
t
EHICCL
PD
Switching Waveforms
Notes
4. WE must be High during SRAM Read cycles.
5. I/O state assumes CE and OE < V
6. Measured ± 200 mV from steady state output voltage.
Document Number: 001-51001 Rev. *A
Description
Figure 6. SRAM Read Cycle 1: Address Controlled
Figure 7. SRAM Read Cycle 2: CE and OE Controlled
and WE > V
; device is continuously selected.
IL
IH
STK11C68-5 (SMD5962-92324)
35 ns
45 ns
Min
Max
Min
Max
35
45
35
45
35
45
15
20
5
5
5
5
13
15
0
0
13
15
0
0
35
45
[4, 5]
[4]
55 ns
Unit
Min
Max
55
ns
55
ns
55
ns
35
ns
5
ns
5
ns
25
ns
0
ns
25
ns
0
ns
55
ns
Page 7 of 15
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