ComBlock COM-1826 Manual - Página 11

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synchronized

0 = not synchronized or no input

1 = synchronized

Signal presence

SREG36(4)

0 = no carrier detected in FFT

1 = carrier detected in FFT

Decoder1 built-in

The Viterbi decoder computes the BER on

BER

the received (encoded) data stream

irrespective of the transmitted bit stream.

Encoded stream bit errors detected over a

1000-bit measurement window.

SREG37 LSB

SREG38 MSB

Decoder2 built-in

The Viterbi decoder computes the BER on

BER

the received (encoded) data stream

irrespective of the transmitted bit stream.

Encoded stream bit errors detected over a

1000-bit measurement window.

SREG39 LSB

SREG40 MSB

Nominal center

Expected center frequency: sum of the

frequency

fixed center frequency and the dynamic

frequency profile

SREG41 (LSB) – SREG44 (MSB)

Carrier frequency

Residual frequency offset with respect to

offset1

the nominal carrier frequency (i.e. after

frequency profile correction). Part 1/2.

32-bit signed integer expressed as

fcerror * * 2

SREG45 (LSB) – SREG48 (MSB)

Carrier frequency

Residual frequency offset with respect to

offset2

the nominal carrier frequency (i.e. after

frequency profile correction). Part 2/2.

32-bit signed integer expressed as

fcerror * * 2

SREG49 (LSB) – SREG52 (MSB)

Despread signal

Average signal power after despreading.

power S

Compute the signal to noise ratio after

despreading as S/N. The absolute value is

meaningless because of multiple agcs.

SREG53 (LSB) – SREG54 (MSB)

Noise power N

Average noise power. Used to compute the

SNR after despreading. The absolute value

is meaningless because of multiple agcs.

SREG55 (LSB) – SREG56 (MSB)

SNR

2*(S+N)/N ratio,

valid only during code lock.

Linear (not in dBs)

Fixed point format 14.2

SREG57 (LSB) – SREG58 (MSB)

table.

clk_p

chip_rate

Bit error rate

Monitors the BER (number of bit

errors on the I- or Q-channel at the

demodulator output, counted over

80,000 received bits) when the

modulator is sending a PRBS-11 test

sequence.

Note: because the demodulator

inherent phase ambiguity, a zero

BER can be displayed as 0 or 80000

(x13880)

SREG59: LSB

SREG60: MSB

BER tester synchronized

SREG36(5): 1 when the BER tester

is synchronized with the received

PRBS-11 test sequence.

Built-in modulator SNR calibration

Parameters

Monitoring

Measured modulated

SREG61(LSB)

signal power

SREG62

SREG63(MSB)

Measured AWGN

SREG64(LSB)

power (Noise

SREG65

bandwidth is 6.25

SREG66(MSB)

MHz)

FPGA configuration options

Parameters

Monitoring

MODULATOR_EN

Indicates whether the modulator is

instantiated (1) or not (0) in the

current active FPGA configuration.

SREG67(0)

ADCs_EN

Demodulator ADC interface

instantiated (1) or not (0)

SREG67(1)

DACs_EN

Modulator DAC interface

instantiated (1) or not (0)

SREG67(2)

AWGN_EN

Additive white Gaussian noise

instantiated (1) or not (0)

SREG67(3)

Multi-byte status variables are latched upon (re-)reading

SREG7.