Bose Lifestyle 28 Manual de solución de problemas - Página 30

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Integrated Circuit Diagrams

DSP ADSP21065LKS, part number 254191-001

Type

SDCLK 1-0

I/O/S/T

SDRAM 2x Clock Output. In systems with multiple SDRAM devices connected in

parallel, supports the corresponding increase clock load requirements, eliminating

need of off-chip clock buffers. Either SDCLK 1 , or both SDCLKx pins can be tri-

stated.

_____

I/O/T

SDRAM Write Enable. in conjunction with CAS MSx, RAS, SDCLKx and

SWDE

sometimes SDA10, defines the operation for the SDRAM to perform.

DQM

O/T

SDRAM Data Mask. In write mode DQM has a latency of zero and is used to block

write operations.

SDCKE

I/O/T

SDRAM Clock Enable. Enables and disables the CLK signal.

SDA10

O/T

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a

host access.

XTAL

Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the ADSP-

21065L's internal clock generator or to disable it to use an external clock source.

See CLKIN

________

I/O/A

PWM Output Event Capture. In PWMOUT mode, is an output pin and functions

PWM_EV

as a timer counter. In WIDTH_CNT mode, is an input pin and function as a pulse

ENT 1-0

counter.event capture.

VDD

Power Supply; Nominally +3.3Vdc (33pins)

GND

Power Supply Return. (30 Pins)

Not Connect. Reserved pins which must be left open and unconnected

PS18/28/35 Troubleshooting Guide

Function