Alinx FL1010 Manual del usuario - Página 7

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C15

C18

C19

C22

C23

C26

C27

C30

C31

C34

C35

C37

D11

D12

D14

D15

D17

D18

D20

D21

D23

D24

D26

D27

D32

D35

Part 2.3: 40-Pin Expansion Ports

The pin definition of the 40-pin header is the same as that of the ALINX

FPGA development board. PIN1, PIN37, and PIN38 are GND, PIN2 is +5V, and

PIN39 and PIN40 are 3.3V; Others are IO ports, and the level standard of IO

ports is determined by the FPGA development board.

7 / 8

FMC to 2*40-Pin Expansion Ports FL1010 User Manual

LA10_N

LA14_P

LA14_N

LA18_P

LA18_N

LA27_P

LA27_N

SCL

SDA

GA0

+12V

GBTCLK0_M2C_P

GBTCLK0_M2C_N

LA01_P

LA01_N

LA05_P

LA05_N

LA09_P

LA09_N

LA13_P

LA13_N

LA17_P

LA17_N

LA23_P

LA23_N

LA26_P

LA26_N

+3.3V

GA1

PIN 29 of J3

PIN 24 of J3

PIN 23 of J3

PIN 6 of J2

PIN 5 of J2

PIN 12 of J2

PIN 11 of J2

EEPROM Clock

EEPROM Data

Low Bit of EEPROM Address

+12V Power Supply

SMA Connector J8

SMA Connector J9

PIN 36 of J3

PIN 35 of J3

PIN 32 of J3

PIN 31 of J3

PIN 28 of J3

PIN 27 of J3

PIN 26 of J3

PIN 25 of J3

PIN 4 of J2

PIN 3 of J2

PIN 8 of J2

PIN 7 of J2

PIN 10 of J2

PIN 9 of J2

+3.3V Power Supply

The Second Bit of EEPROM Address