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Fujitsu PRIMERGY RX300 S8 Manual de instrucciones
4. Rank Sparing Mode
1-Rank Memory modules (RDIMM)
Channel
C hannel
A
Bank I
Spare
Spare
(black sockets)
Bank II
Data
Data
(blue sockets)
Bank III
Data
Data
(green sockets)
1st
XEON CPU
2-Rank Memory modules (RDIMM)
Channel
Channel
A
Bank I
R1
Spare
Spare
(black)
R2
Data
Data
Bank II
R1
Data
Data
(blue)
R2
Data
Data
Bank III
R1
Data
Data
(green)
R2
Data
Data
1st
XEON CPU
4-Rank Memory modules (LRDIMM)
Channel
C hannel
A
Bank I
R1
Spare
Spare
(black)
R2
Data
Data
R3
Data
Data
R4
Data
Data
Bank II
R1
Data
Data
(blue)
R2
Data
Data
R3
Data
Data
R4
Data
Data
Bank III
R1
Data
Data
(green)
R2
Data
Data
R3
Data
Data
R4
Data
Data
1st
XEON CPU
Rank Sparing Mode requires identical modules (same capacity and technology) within the same channel.
The available memory for applications will vary depending on configuration. Please refer to the spreadsheet above
"Effective Memory capacity with active Rank Sparing Mode". Population rule for Rank sparing mode is to achieve max.
available memory, e.g. 6 DIMMs will be spread across two channels, each with 3DPC
B
Channel
C
Channel
D
Channel
Spare
Spare
Spare
Data
Data
Data
Data
Data
Data
(4/6/8 Core)
2nd
B
Channel
C
Channel
D
Channel
Spare
Spare
Spare
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
(4/6/8 Core)
2nd
B
Channel
C
Channel
D
Channel
Spare
Spare
Spare
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
(4/6/8 Core)
2nd
Fujitsu PRIMERGY Server
System configurator and order-information guide
PRIMERGY RX300 S8
Channel
E
C hannel
F
C hannel
G
Spare
Spare
Spare
Data
Data
Data
Data
Data
Data
XEON CPU
(4/6/8) Core)
Channel
E
Channel
F
C hannel
G
Spare
Spare
Spare
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
XEON CPU
(4/6/8) Core)
Channel
E
C hannel
F
C hannel
G
Spare
Spare
Spare
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
XEON CPU
(4/6/8) Core)
Status 2017-02-28
required
required if 2nd CPU is configured
H
optional, same type in Channel per CPU
optional, any type
-------- not used
H
required
required if 2nd CPU is configured
optional, same type in Channel per CPU
optional, any type
-------- not used
H
required
required if 2nd CPU is configured
optional, same type in Channel per CPU
optional, any type
-------- not used
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