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Fujitsu MB91460 SERIES Nota de aplicación

REVISION HISTORY ............................................................................................................ 2

WARRANTY AND DISCLAIMER ......................................................................................... 3

CONTENTS .......................................................................................................................... 4

1 INTRODUCTION .............................................................................................................. 6

1.1

Key Features ........................................................................................................... 6

2 DIRECT MEMORY ACCESS ........................................................................................... 7

2.1

Block Diagram ......................................................................................................... 7

2.2

Outline ..................................................................................................................... 8

2.2.1

Single Transfer .......................................................................................... 8

2.2.2

Multiple Transfers ...................................................................................... 9

2.3

Registers ............................................................................................................... 10

2.3.1

Control/Status Registers A (DMACA0-4) .................................................. 10

2.3.2

Control/Status Registers B (DMACB0-4) .................................................. 11

2.3.3

Transfer Source Address Setting Register (DMASA0-4)........................... 12

2.3.4

Transfer Destination Address Setting Register (DMADA0-4) .................... 12

2.3.5

DMAC All-Channel Control Register (DMACR) .......................................... 13

2.4

Operation .............................................................................................................. 14

2.4.1

Transfer Mode ......................................................................................... 14

2.4.1.1

2.4.1.2

2.4.1.3

2.4.1.4

2.4.2

Transfer Type .......................................................................................... 16

2.4.2.1

2.4.2.2

2.4.3

DMA Transfer and Interrupts.................................................................... 16

2.4.4

External Transfer Requests ..................................................................... 17

2.4.5

External Bus Request Arbitration (BRQ) .................................................. 18

3 DMAC EXAMPLES ........................................................................................................ 19

3.1

DMAC Example with External Bus......................................................................... 19

3.2

DMAC Example with UART ................................................................................... 25

4 ADDITIONAL INFORMATION ....................................................................................... 27

LIST OF FIGURES ............................................................................................................. 28

MCU-AN-300059-E-V11

DIRECT MEMORY ACCESS

Contents

Step Transfer ........................................................................... 14

Block Transfer .......................................................................... 14

Burst Transfer .......................................................................... 15

Demand Transfer ..................................................................... 15

2-cycle Transfer ....................................................................... 16

Fly-by Transfer ......................................................................... 16

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