Fujitsu MB91460 SERIES Nota de aplicación - Página 15
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Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3.1 Clock source (CLOCKSOURCE, ENABLE_SUBCLOCK)
The clock source of the base clock can be configured in the following.
Main Clock SV
Cntr.
Mai
n
Logic
Os
cillator
1
4 MHz
0
CSVCR_
MSVE
Su
b
Os
cillator
Sub Clock SV
0
32 kHz
1
CSVCR_
SSVE
Cntr.
RC
Logic
Oscillator
CSVCR
100 kHz
RC
0
Oscillator
1
CSCFG_
2 MHz
RCSEL
Available settings for CLOCKSOURCE:
- NOCLOCK
- MAINCLOCK
- MAINPLLCLOCK
- SUBCLOCK
Available settings for ENABLE_SUBCLOCK:
- ON
- OFF
Example:
The PLL should be used and the sub clock should not be enabled.
#set CLOCKSOURCE
#set ENABLE_SUBCLOCK OFF
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
1/2
PLL Interface x1, x2, ...x25
1/G
Auto-Gear
PLL
x
CLKVCO
1/M
1/N
FB
CLKPLLFB
0
Multiplier
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
CSVCR_
SCKS
The clock register are not set by the startup code
MB91461R: Base clock frequency = ¼ of main clock
Others:
Base clock frequency = ½ of main clock
The PLL (programmable) is used as base clock
Te sub clock is selected as base clock
Enable sub clock
Sub clock is not enabled
MAINPLLCLOCK ;<<< Clocksource
CLKPLL
Clock
0
1
Modulator
1
CMCR, CMPR
2
0
CMCR_
3
CLKR_
FMOD
CLKS
0
3
1
CANPRE_
CPCKS
;<<< Subclock: ON/OFF
- 15 -
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
Φ
Base Clock
Ext. Bus Clock
CLKT
Divider /1 .. /16
DIV1R
Peripheral Clock
CLKP
Divider /1 .. /16
DIV0R
CPU Clock
CLKB
Divider /1 .. /16
DIV0R
CAN Clock
CANCLK
Divider /1 .. /16
CANPRE
MCU-AN-300021-E-V10