Dell™ PowerEdge™ M710 Technical Guidebook
b. DiMMs supported
The DDR3 memory interface consists of three channels, with up to two RDIMMs or UDIMMs per chan-
nel for single-/dua- rank and up to two RDIMMs per channel for quad rank. The interface uses 2GB, 4GB,
or 8GB RDIMMs. 1GB or 2GB UDIMMs are also supported. The memory mode is dependent on how the
memory is populated in the system:
Three channels per CPU populated identically
• T ypically, the system will be set to run in Memory Optimized (Independent Channel) mode in
this configuration. This mode offers the most DIMM population flexibility and system memory
capacity, but offers the least number of RAS (reliability, availability, service) features.
• A ll three channels must be populated identically.
• U sers wanting memory sparing must also populate the DIMMs in this method, but one channel
is the spare and is not accessible as system memory until it is brought online to replace a failing
channel.
• T he first two channels per CPU populated identically with the third channel unused
• T ypically, two channels operate in Advanced ECC (Lockstep) mode with each other by
having the cache line split across both channels. This mode provides improved RAS
features (SDDC support for x8-based memory).
• F or Memory Mirroring, two channels operate as mirrors of each other — writes go to
both channels and reads alternate between the two channels.
• O ne channel per CPU populated
• T his is a simple Memory Optimized mode. No mirroring or sparing is supported.
The PowerEdge M710 memory interface supports memory demand and patrol scrubbing, single-bit
correction and multi-bit error detection. Correction of a x4 or x8 device failure is also possible with
SDDC in the Advanced ECC mode. Additionally, correction of a x4 device failure is possible in the
Memory Optimized mode. If DIMMs of different speeds are mixed, all channels will operate at the fastest
common frequency. RDIMMs and UDIMMs cannot be mixed.
• I f memory mirroring is enabled, identical DIMMs must be installed in the same slots across both
channels.
• T he third channel of each processor is unavailable for memory mirroring.
• T he first DIMM slot in each channel is color-coded with white ejection tabs for ease of
installation.
• T he DIMM sockets are placed 450 mils (11.43 mm) apart, center-to-center in order to provide
enough space for sufficient airflow to cool stacked DIMMs.
• T he PE M710 memory system supports up to 18 DIMMs. DIMMs must be installed in each channel
starting with the DIMM farthest from the processor. Population order will be identified by the
silkscreen designator and the System Information Label (SIL) located on the chassis cover.
• M emory Optimized: {1, 2, 3}, {4, 5, 6}, {7, 8, 9}
• A dvanced ECC or Mirrored: {2, 3}, {5, 6}, {8, 9}
• Q uad Rank or UDIMM: {1, 2, 3}, {4, 5, 6}, {7, 8, 9}
c. speed
Memory Speed Limitations
The memory frequency is determined by a variety of inputs:
• S peed of the DIMMs
• S peed supported by the CPU
• C onfiguration of the DIMMs
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