HP 386819-001 - ProSignia - 720 Visión general - Página 18
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Rambus DRAM
Rambus DRAM (RDRAM) allows data transfer through a bus operating in a higher frequency range
than DDR SDRAM. In essence, Rambus moves small amounts of data very fast, whereas DDR SDRAM
moves large amounts of data more slowly. The Rambus design consists of three key elements:
RDRAMs, Rambus application-specific integrated circuits, and an interconnect called the Rambus
Channel. The Rambus design provides higher performance than traditional SDRAM because RDRAM
transfers data on both edges of a synchronous, high-speed clock pulse. RDRAM uses a separate row
and column command bus that allows multiple commands to be issued at the same time, thereby
increasing the bandwidth efficiency of the memory bus. This dual command bus is a unique feature of
RDRAM.
With only an 8-bit-wide command bus and an 18-bit data bus, RDRAM (Figure 17) has the lowest
signal count of all of the memory technologies. RDRAM incorporates a packet protocol and is capable
of operating at 800 MHz and providing a peak bandwidth of 2.4 GB/s. One packet of information
is transferred in 8 ticks of the clock, which allows sending128 bits of data in a 150-MHz clock
period. Since it requires 8 ticks of the clock to transfer a packet, the internal memory controller only
needs to run at a speed of 150 MHz to keep up with the packet transfer rate at 1.2 GHz. This allows
for plenty of timing margin in the design of the memory controller.
Figure 17. Rambus DRAM
RDRAM is capable of supporting up to 32 RDRAM devices on one memory channel while maintaining
a 1.2-GHz data rate. Through the use of a repeater chip, even more devices can be placed on one
RDRAM channel. The repeater will interface to two different RDRAM channels and pass the data and
command signals between them. One channel will communicate with the memory controller, and the
other channel will communicate with the RDRAM devices. Thus, the memory controller essentially will
be communicating only with the repeater chips. Up to eight repeater chips can be placed on the
memory controller, and 32 RDRAM devices can be placed on each channel. This allows one channel
to support a maximum of 256 devices. However, using the repeater chips will add 1 to 1.5 clocks of
additional delay.
To account for differences in distance of the devices on the channel, more latency in increments of the
clock can be added. This allows the memory controller to receive data from all devices in the same
amount of time, thus preventing data collision on the bus when consecutive reads are performed to
different devices.
Another feature of RDRAM that helps to increase the efficiency is an internal 128-bit write buffer. All
write data is placed into this buffer before being sent to the DRAM core. The write buffer reduces the
delay needed to turn around the internal data bus by allowing the sense amps to remain in the read
direction until data needs to be retired from the buffer to the core. Essentially, a read can immediately
follow a write with little bandwidth lost on the data bus.
While the RDRAM bus efficiency is high, the packet protocol increases the latency. The packet
translation between the internal memory controller bus and the fast external bus requires one to two
clocks of additional delay. This delay cannot be avoided when using a very fast packet protocol.
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