Dialog Semiconductor SLG46824 Manual de programación - Página 8

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1. Hardware Requirements

ISPG-SLG46824/6

SLG46824/6

3.1.3 Erase Command

The erase scheme allows a 16 byte page in the emulated EEPROM

to be erased by modifying the contents of the Erase Register (ERSR). When the ERSE bit is set in the ERSR register, the device

will start a self-timed erase cycle which will complete in a maximum of t

accomplished with a Byte Write sequence with the requirements outlined in this section. The ERSR register is located on the E3H

address.

Note 2: Emulated EEPROM is available for SLG46826 only.

Table 2: Erase Register Bit format

Page Erase

ERSE

Table 3: Erase Register Bit Function Description

Bit

Name

ERSE

ERSEB4

ERSEB3

ERSEB2

Selection

for Erase

ERSEB1

ERSEB0

Upon receipt of the proper Device Address and Erase Register Address, the SLG46824/6 will send an ACK. The device will then

be ready to receive Erase Register data. The SLG46824/6 will respond with a non-compliant I

data word is received. Please reference the SLG46824/6 errata document (revision XC) posted on Dialog's website for more

information. The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition. At that

time, the GPAK will enter an internally self-timed erase cycle, which will be completed within t

being written into the Memory Array, all inputs, outputs, internal logic and I

operational/valid.

After the erase has taken place, the contents of ERSE bits will be set to "0" automatically. Erase will be triggered by Stop Bit in

C command.

3.2 ADDRESSING

Each command to the I

C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are

shown in

Figure

7. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced

independently from the register or by value defined externally by IO5, IO4, IO3 and IO2. The LSB of the control code is defined

by the value of IO2, while the MSB is defined by the value of IO5. The address source (either register bit or PIN) for each bit in

the control code is defined by reg <1623:1620>. This gives the user flexibility on the chip level addressing of this device and

other devices on the same I

which will define the most significant bits in the addressing of the data to be read or written by the command. The last bit in the

Control Byte is the R/W bit, which selects whether a read command or write command is requested, with a "1" selecting for a

Read command, and a "0" selecting for a Write command. This Control Byte will be followed by an Acknowledge bit (ACK),

which is sent by this device to indicate successful communication of the Control Byte data

Type

Description

Erase

Setting b7 bit to "1" will start in internal erase cycle on the page defined

Enable

by ERSEB4-0

Page

Define the page address, which will be erased.

ERSB4 = 0 corresponds to the Upper 2K NVM used for chip configuration;

ERSB4 = 1 corresponds to the 2-k emulated EEPROM

C bus. The default control code is 0001. The Block Address is the next three bits (A10,A9, A8),

Revision 1.1

(Note 2)

space or the 2K bits NVM chip configuration space

= 20 ms (max). Changing the state of the ERSR is

ERSEB4

ERSEB3

ERSEB2

C access to the Register data will be

8 of 15

ERSEB1

(Note

2).

C ACK after the Erase Register

(max 20 ms). While the data is

4-Mar-2019

ERSEB0