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Pmod CAN Reference Manual



Bit 2 is TXREQ Message Transmit request bit (bit 3 in TXB0CTRL register 0x30) auto cleared on

message sent



Bit 1* is RX1IF Receive Buffer 1 Empty interrupt Flag bit (bit 1 in CANINTF (0x2C)), must be

cleared by system to be reset



Bit 0* (LSB) is RX0IF Receive Buffer 0 Empty interrupt Flag bit (bit 0 in CANINTF (0x2C)), must be

cleared by system to be reset



*-These interrupt flags are disabled by default in the CAN Interrupt Enable register (address

0x2B)

2. If a receive buffer has data in it, determine the length of the message through the four LSBs of the

associated DLC register for the receive buffer (0x65 for RXB0DLC and 0x75 for RXB1DLC)

3. Reset the interrupt flag that was triggered by clearing bit 0 (RX0IF) or bit 1 (RX1IF) as appropriate in the

CANINTF (0x2C) register after reading the data.

2.3.3 Transmit

1. Load data through a Load TX Buffer SPI command. 6 different starting locations are available



Transmit Buffer 0 starting at the standard identifier high register (0x31) – 0x40



Transmit Buffer 0 starting at the data byte register (0x36) – 0x41



Transmit Buffer 1 starting at the standard identifier high register (ox41) – 0x42



Transmit Buffer 1 starting at the data byte register (0x46) – 0x43



Transmit Buffer 2 starting at the standard identifier high register (ox51) – 0x44



Transmit Buffer 2 starting at the data byte register (0x56) – 0x45

2. Send a Request-To-Send SPI command for one or more of the three registers of interest



Transmit buffer 0 (TXB0) uses 0x81



Transmit buffer 1 (TXB1) uses 0x82



Transmit buffer 2 (TXB2) uses 0x84



Multiple transmit buffers can be simultaneously primed by OR'ing the SPI commands



Note that this command does not actually initiate a message transmission. The MCP25625 still

internally goes through arbitration on the bus line and only transmits the message when the bus

is available.

3. Upon completion, the bit set to indicate to the controller that a message is ready to be transmitted will be

cleared and an interrupt will be generated if the TXnIE bit in the CANINTE register is set.

Application Information

The CAN protocol uses two communication lines, CANH and CANL, to enable communication between multiple

CAN transceivers called nodes. The two bus lines are actively driven to produce a differential voltage greater than

1.5 V, resulting in the Dominant transmission state. CAN transceivers will interpret a dominant transmission as a

logic low state. A logic high state is created by neither bus driving their lines so that they idle at approximately the

same voltage, typically Vcc/2 as biased by the common mode transceiver. This state is a Recessive transmission

and typically has a differential voltage of less than ±100 mV.

Similar to UART, all nodes on a CAN network must operate at the same nominal bit rate as data is transmitted

without a clock signal in an asynchronous format. The Pmod CAN is compliant with CAN 2.0B (ISO-11898-2 and

ISO-11898-5). In additional to the de-facto RS-232 header, Header J1, screw terminals are provided on Header

J3 for other CAN devices that use twisted pair wiring.

Other product and company names mentioned may be trademarks of their respective owners.

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