Cypress Semiconductor AutoStore STK14CA8 Hoja de especificaciones - Página 5
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SRAM READ Cycles #1 and #2
Symbols
NO.
#1
#2
t
1
ELQV
[3]
[3]
t
t
2
AVAV
ELEH
[4]
[4]
t
t
3
AVQV
AVQV
t
4
GLQV
[4]
[4]
t
t
5
AXQX
AXQX
t
6
ELQX
[5]
t
7
EHQZ
t
8
GLQX
[5]
t
9
GHQZ
[2]
t
10
ELICCH
[2]
t
11
EHICCL
ADDRESS
DQ (DATA OUT)
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured ± 200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles
Document Number: 001-51592 Rev. **
Parameter
Alt.
t
Chip Enable Access Time
ACS
t
Read Cycle Time
RC
t
Address Access Time
AA
t
Output Enable to Data Valid
OE
t
Output Hold after Address Change
OH
t
Address Change or Chip Enable to
LZ
Output Active
t
Address Change or Chip Disable to
HZ
Output Inactive
t
Output Enable to Output Active
OLZ
t
Output Disable to Output Inactive
OHZ
t
Chip Enable to Power Active
PA
t
Chip Disable to Power Standby
PS
Figure 6. SRAM READ Cycle #1: Address Controlled
5
t
AXQX
Figure 7. SRAM READ Cycle #2: E and G Controlled
6
3
4
8
10
STK14CA8-25 STK14CA8-35 STK14CA8-45
Min
Max
25
25
25
12
3
3
10
0
10
0
25
2
t
AVAV
3
t
AVQV
DATA VALID
2
29
1
STK14CA8
Min
Max
Min
Max
35
45
35
45
35
45
15
20
3
3
3
3
13
15
0
0
13
15
0
0
35
45
[3, 4, 6]
[3, 6]
11
7
9
Page 5 of 16
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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