Cypress Semiconductor CY7C0251AV Hoja de especificaciones - Página 9

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3.3V
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
(a) Normal Load (Load 1)

Switching Characteristics

[20]
Over the Operating Range
Parameter
Read Cycle
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Output Hold From Address Change
OHA
[21]
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
[22, 23, 24]
t
OE Low to Low Z
LZOE
[22, 23, 24]
t
OE HIGH to High Z
HZOE
[22, 23, 24]
t
CE LOW to Low Z
LZCE
[22, 23, 24]
t
CE HIGH to High Z
HZCE
[24]
t
CE LOW to Power Up
PU
[24]
t
CE HIGH to Power Down
PD
[21]
t
Byte Enable Access Time
ABE
Write Cycle
t
Write Cycle Time
WC
[21]
t
CE LOW to Write End
SCE
t
Address Valid to Write End
AW
t
Address Hold From Write End
HA
[21]
t
Address Setup to Write Start
SA
Notes
20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
and 30 pF load capacitance.
21. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
22. At any given temperature and voltage condition for any given device, t
23. Test conditions used are Load 3.
24. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to
Document #: 38-06052 Rev. *J
Figure 4. AC Test Loads and Waveforms
R
= 250Ω
TH
OUTPUT
C = 30pF
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
90%
10%
GND
≤
3 ns
Description
is less than t
HZCE
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
OUTPUT
C = 5 pF
V
= 1.4V
TH
(c) Three-State Delay (Load 2)
(Used for t
including scope and jig)
90%
10%
≤
3 ns
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
Min
Max
20
20
3
20
12
3
12
3
12
0
20
20
20
15
15
0
0
and t
is less than t
.
LZCE
HZOE
LZOE
3.3V
R1 = 590Ω
R2 = 435Ω
, t
, t
, and t
LZ
HZ
HZWE
LZWE
Unit
-25
Min
Max
25
ns
25
ns
3
ns
25
ns
13
ns
3
ns
15
ns
3
ns
15
ns
0
ns
25
ns
25
ns
25
ns
20
ns
20
ns
0
ns
0
ns
/I
OI
OH
time.
SCE
Figure
12.
Page 9 of 19
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